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2020 – today
- 2024
[j37]Vinay Malligere Shivanna
, Jiun-In Guo:
Object Detection, Recognition, and Tracking Algorithms for ADASs - A Study on Recent Trends. Sensors 24(1): 249 (2024)- [j36]Yu-Shu Ni, Wei-Lun Chen, Yi Liu, Ming-Hsuan Wu, Jiun-In Guo:
Optimizing Automated Optical Inspection: An Adaptive Fusion and Semi-Supervised Self-Learning Approach for Elevated Accuracy and Efficiency in Scenarios with Scarce Labeled Data. Sensors 24(17): 5737 (2024) - [c124]Yu-Shu Ni, Han-Chun Chen, Chia-Chi Tsai, Chih-Cheng Chen, Po-Yu Chen, Hsien-Kai Kuo, Jun-Ying Hunag, Po-Chi Hu, Jenq-Neng Hwang, Jiun-In Guo:
Summary of the 2024 Low-Power Efficient and Accurate Facial-Landmark Detection for Embedded Systems. ICME Workshops 2024: 1-6 - 2023
- [j35]Jia-Jheng Lin, Jiun-In Guo, Vinay Malligere Shivanna, Ssu-Yuan Chang:
Deep Learning Derived Object Detection and Tracking Technology Based on Sensor Fusion of Millimeter-Wave Radar/Video and Its Application on Embedded Systems. Sensors 23(5): 2746 (2023) - [j34]Bo-Hong Lin, Vinay Malligere Shivanna, Jiun-Shiung Chen, Jiun-In Guo:
360° Map Establishment and Real-Time Simultaneous Localization and Mapping Based on Equirectangular Projection for Autonomous Driving Vehicles. Sensors 23(12): 5560 (2023) - [c123]Yi-Chiao Fang, Xi-Liang Zhao, Hsuan-Yu Lin, Yu-Cheng Yang, Jiun-In Guo, Chih-Peng Fan:
YOLO Deep-Learning Based Driver Behaviors Detection and Effective Gaze Estimation by Head Poses for Driver Monitor System. GCCE 2023: 82-83 - [c122]Yu-Shu Ni, Chia-Chi Tsai, Chih-Cheng Chen, Hsien-Kai Kuo, Po-Yu Chen, Po-Chi Hu, Ted T. Kuo, Jenq-Neng Hwang, Jiun-In Guo:
Summary of the 2023 Low-Power Deep Learning Object Detection and Semantic Segmentation Multitask Model Compression Competition for Traffic Scene in Asian Countries. ICME Workshops 2023: 34-39 - [c121]Po-Yuan Chen, Hung-Che Lin, Jiun-In Guo:
Multi-Scale Dynamic Fixed-Point Quantization and Training for Deep Neural Networks. ISCAS 2023: 1-5 - [c120]Cheng-Fu Liou, Tsung-Han Lee, Jiun-In Guo:
Asynchronous Multi-Task Learning Based on One Stage YOLOR Algorithm. ISIE 2023: 1-5 - [c119]Yu-Shu Ni, Chia-Chi Tsai, Jyun-Syu Lin, Hsien-Po Meng, Po-Chi Hu, Jiun-Shiung Chen, Kun-Hung Lin, Chih-Yuan Chuang, Jiun-In Guo:
Summary of the 2023 PAIR-LITEON Competition: Embedded AI Object Detection Model Design Contest on Fish-eye Around-view Cameras. MMAsia 2023: 113:1-113:7 - 2022
- [j33]Hung-Wei Lin, Vinay Malligere Shivanna, Hsiu Chi Chang, Jiun-In Guo:
Real-Time Multiple Pedestrian Tracking With Joint Detection and Embedding Deep Learning Model for Embedded Systems. IEEE Access 10: 51458-51471 (2022) - [j32]Yu-Shu Ni, Vinay Malligere Shivanna, Jiun-In Guo:
iVS Dataset and ezLabel: A Dataset and a Data Annotation Tool for Deep Learning Based ADAS Applications. Remote. Sens. 14(4): 833 (2022) - [j31]Bo-Xun Wu, Vinay Malligere Shivanna, Hsiang-Hsuan Hung, Jiun-In Guo:
ConcentrateNet: Multi-Scale Object Detection Model for Advanced Driving Assistance System Using Real-Time Distant Region Locating Technique. Sensors 22(19): 7371 (2022) - [j30]Chia-Chi Tsai, Jiun-In Guo:
IVS-Caffe - Hardware-Oriented Neural Network Model Development. IEEE Trans. Neural Networks Learn. Syst. 33(10): 5978-5992 (2022) - [c118]Bo-Xun Wu, Jia-Jheng Lin, Hsien-Kai Kuo, Po-Yu Chen, Jiun-In Guo:
Radar and Camera Fusion for Vacant Parking Space Detection. AICAS 2022: 242-245 - [c117]Yu-Shu Ni, Chia-Chi Tsai, Chih-Cheng Chen, Po-Yu Chen, Hsien-Kai Kuo, Man-Yu Lee, Kuo Chin-Chuan, Zhe-Ln Hu, Po-Chi Hu, Ted T. Kuo, Jenq-Neng Hwang, Jiun-In Guo:
Summary of the 2022 Low-Power Deep Learning Semantic Segmentation Model Compression Competition for Traffic Scene In Asian Countries. ICME Workshops 2022: 1-6 - [c116]An-Tai Hsiao, Chun-Hsien Liu, Po-Hsuan Chen, Yao-Lun Liu, Wei-Chi Wang, Tzu-Hsien Sang, Chia-Ming Tsai, Gray Lin, Jiun-In Guo, Sheng-Di Lin:
Real-time LiDAR module with 64x128-pixel CMOS SPAD array and 940-nm PCSEL. SAS 2022: 1-6 - 2021
- [j29]Chun-Yu Lai, Bo-Xun Wu, Vinay Malligere Shivanna, Jiun-In Guo:
MTSAN: Multi-Task Semantic Attention Network for ADAS Applications. IEEE Access 9: 50700-50714 (2021) - [j28]Zohauddin Ahmad, Yan-Min Liao, Sheng-I Kuo, You-Chia Chang, Rui-Lin Chao, Naseem, Yi-Shan Lee, Yung-Jr Hung, Huang-Ming Chen, Jyehong Chen, Jiun-In Guo, Jin-Wei Shi:
High-Power and High-Responsivity Avalanche Photodiodes for Self-Heterodyne FMCW Lidar System Applications. IEEE Access 9: 85661-85671 (2021) - [j27]Tzu-Hsien Sang, Feng-Tsun Chien, Chia-Chih Chang, Kuan-Yu Tseng, Bo-Sheng Wang, Jiun-In Guo:
DoA Estimation for FMCW Radar by 3D-CNN. Sensors 21(16): 5319 (2021) - [c115]Cheng-Fu Liou, Li-Ting Huang, Paul Kuo, Chien-Kuo Wang, Jiun-In Guo:
AI-Assisted Stanford Classification of Aortic Dissection in CT Imaging Using Volumetric 3D CNN with External Guided Attention. BioCAS 2021: 1-5 - [c114]Tsung-Han Lee, Li-Ting Huang, Paul Kuo, Chien-Kuo Wang, Jiun-In Guo:
Focal-Balanced Attention U-Net with Dynamic Thresholding by Spatial Regression for Segmentation of Aortic Dissection in CT Imagery. ISBI 2021: 541-544 - [c113]Cheng-Fu Liou, Paul Kuo, Jiun-In Guo:
Residual Knowledge Retention For Edge Devices. ISIE 2021: 1-6 - [c112]Yu-Shu Ni, Chia-Chi Tsai, Jiun-In Guo, Jenq-Neng Hwang, Bo-Xun Wu, Po-Chi Hu, Ted T. Kuo, Po-Yu Chen, Hsien-Kai Kuo:
Summary of the 2021 Embedded Deep Learning Object Detection Model Compression Competition for Traffic in Asian Countries. ICMR 2021: 244-249 - 2020
- [j26]Jiun-In Guo, Chia-Chi Tsai, Jian-Lin Zeng, Shao-Wei Peng, En-Chih Chang:
Hybrid Fixed-Point/Binary Deep Neural Network Design Methodology for Low-Power Object Detection. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 388-400 (2020) - [j25]Guan-Ting Lin, Vinay Malligere Shivanna, Jiun-In Guo:
A Deep-Learning Model with Task-Specific Bounding Box Regressors and Conditional Back-Propagation for Moving Object Detection in ADAS Applications. Sensors 20(18): 5269 (2020) - [c111]Jian Xian Lu, Jia-Cheng Lin, M. S. Vinay, Po-Yu Chen, Jiun-In Guo:
Fusion Technology of Radar and RGB Camera Sensors for Object Detection and Tracking and its Embedded System Implementation. APSIPA 2020: 1234-1242 - [c110]Chia-Chi Tsai, Yong-Hsiang Yang, Hung-Wei Lin, Bo-Xun Wu, En-Chih Chang, Hung Yu Liu, Jhih-Sheng Lai, Po Yuan Chen, Jia-Jheng Lin, Jen Shuo Chang, Li-Jen Wang, Ted T. Kuo, Jenq-Neng Hwang, Jiun-In Guo:
The 2020 Embedded Deep Learning Object Detection Model Compression Competition for Traffic in Asian Countries. ICME Workshops 2020: 1-6 - [c109]Yu-Ting Li, Paul Kuo, Jiun-In Guo:
Automatic Industry PCB Board DIP Process Defect Detection with Deep Ensemble Method. ISIE 2020: 453-459 - [c108]Wen-Chia Tsai, Kuan-Chou Chen, Jhih-Sheng Lai, Jiun-In Guo:
Front Moving Object Behavior Prediction System Exploiting Deep Learning Technology for ADAS Applications. MWSCAS 2020: 1052-1055 - [c107]Ching-Hwa Cheng, Jiun-In Guo:
Low-Power 3D-PCB Stacking System Design and Validation by Automatic Voltage-Current Scalable Technique. VLSI-DAT 2020: 1-2 - [c106]Zi-Yi Zhao, An-Tai Xiao, Jiun-In Guo:
Video Dehazing Hardware Accelerator Design based on Dark Channel Prior with Sky Preservation. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [c105]Yi-Hsuan Hsu, Jiun-In Guo:
A Real-time and Online Multiple-Type Object Tracking Method with Deep Features. APSIPA 2019: 1922-1928 - [c104]Ching-Kai Tseng, Chien-Chih Liao, Po-Chun Shen, Jiun-In Guo:
Using C3D to Detect Rear Overtaking Behavior. ICIP 2019: 151-154 - [c103]Kuan-Chou Chen, Guan-Ting Lin, Che-Tsung Lin, Jiun-In Guo:
Recognizing Chinese Texts with 3D Convolutional Neural Network. ICIP 2019: 2120-2123 - [c102]Jiun-In Guo, Chia-Chi Tsai, Yong-Hsiang Yang, Hung-Wei Lin, Bo-Xun Wu, Ted T. Kuo, Li-Jen Wang:
Summary Embedded Deep Learning Object Detection Model Competition. MMSP 2019: 1-5 - [c101]Jiun-In Guo, Chi-Chi Tsai, Ching-Kan Tseng:
Pvalite CLN: Lightweight Object Detection with Classfication and Localization Network. SoCC 2019: 118-121 - 2018
- [c100]Guan-Ting Lin, Patrisia Sherryl Santoso, Che-Tsung Lin, Chia-Chi Tsai, Jiun-In Guo:
One Stage Detection Network with an Auxiliary Classifier for Real-Time Road Marks Detection. APSIPA 2018: 1379-1382 - [c99]Chia-Chi Tsai, Ching-Kan Tseng, Ho-Chia Tang, Jiun-In Guo:
Vehicle Detection and Classification based on Deep Neural Network for Intelligent Transportation Applications. APSIPA 2018: 1605-1608 - [c98]Shun-Min Chang, Chia-Chi Tsai, Jiun-In Guo:
A Blind Spot Detection Warning System based on Gabor Filtering and Optical Flow for E-mirror Applications. ISCAS 2018: 1-5 - 2017
- [c97]Guan-Ting Lin, Patrisia Sherryl Santoso, Che-Tsung Lin, Chia-Chi Tsai, Jiun-In Guo:
Stop line detection and distance measurement for road intersection based on deep learning neural network. APSIPA 2017: 692-695 - [c96]Yuan-Fu Li, Chia-Chi Tsai, Yi-Ting Lai, Jiun-In Guo:
A multiple-lane vehicle tracking method for forward collision warning system applications. APSIPA 2017: 1061-1064 - [c95]Tai-En Wu, Chia-Chi Tsai, Jiun-In Guo:
LiDAR/camera sensor fusion technology for pedestrian detection. APSIPA 2017: 1675-1678 - [c94]Chuan-Chung Chang, Hsin-Hsiang Lo, Han-Hsuan Lin, Zhi-Rong Fan, Shao-Hsuan Cheng, Chih-Hung Lu, Fu-Ming Chuang, Jiun-In Guo:
Localized High Dynamic Range Plenoptic Image Compression. Computational Imaging 2017: 163-168 - [c93]Fong-An Chang, Chia-Chi Tsai, Ching-Kan Tseng, Jiun-In Guo:
Embedded multiple object detection based on deep learning technique for advanced driver assistance system. MWSCAS 2017: 172-175 - [c92]Ricky Lee, Tai en Wu, Jiun-In Guo:
An Adaptive Cross-Window stereo camera Distance Estimation technology and its system implementation for multiple applications. VLSI-DAT 2017: 1-4 - [c91]Chia-Chi Tsai, Yi-Ting Lai, Yuan-Fu Li, Jiun-In Guo:
A vision radar system for car safety driving applications. VLSI-DAT 2017: 1-4 - 2016
- [c90]An-Tai Xiao, Yung-Siang Miao, Ching-Hwa Cheng, Jiun-In Guo:
A variable-voltage low-power technique for digital circuit system. ASP-DAC 2016: 13-14 - [c89]Yi-Ting Lin, Ting Chou, M. S. Vinay, Jiun-In Guo:
Algorithm derivation and its embedded system realization of speed limit detection for multiple countries. ISCAS 2016: 2555-2558 - 2015
- [c88]Bing-Yang Cheng, Jui-Sheng Lee, Jiun-In Guo:
An AdaBoost object detection design for heterogeneous computing with OpenCL. ICCE-TW 2015: 286-287 - [c87]Yu-Fu Lin, Wei-Min Lu, Kuan-Hung Chen, Jiun-In Guo:
Vision-based landing system design for a small UAV. ICCE-TW 2015: 496-497 - [c86]Ching-Hwa Cheng, Sheng-Ping Hung, Jiun-In Guo, Kai-Che Liu, Jungle Chi-Hsiang Wu:
A wireless panoramic endoscope system design and implementation for minimally invasive surgery. ISCAS 2015: 1895 - [c85]Po-Yu Chien, Yuan-Hsiang Miao, Jiun-In Guo:
A 3D hand tracking design for gesture control in complex environments. VLSI-DAT 2015: 1-4 - [c84]An-Tia Xiao, Shiang-Ren Yang, Yuan-Hsiang Miao, Ching-Hwa Cheng, Jiun-In Guo:
A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applications. VLSI-DAT 2015: 1-4 - 2014
- [c83]Po-Hsiang Huang, Yuan-Hsiang Miao, Jiun-In Guo:
High dynamic range imaging technology for micro camera array. APSIPA 2014: 1-4 - [c82]Che-Cheng Li, Sheng-Wei Hsu, Po-Chun Shen, Jiun-In Guo:
A single-camera high dynamic range technique by using contrast enhancement and exposure control. APSIPA 2014: 1-4 - [c81]Chingwei Yeh, Chen-Yao Tsai, Tay-Jyi Lin, Jiun-In Guo:
Maintaining color fidelity for dual-shot HDR imaging. ICCE-TW 2014: 65-66 - [c80]Sheng-Wei Hsu, Guan-Yu Chen, Po-Chun Shen, Chao-Yi Cho, Jiun-In Guo:
Dynamic local contrast enhancement for advanced driver assistance system in harsh environments. ICCE-TW 2014: 69-70 - [c79]Ting-Fung Ju, Wei-Min Lu, Kuan-Hung Chen, Jiun-In Guo:
Vision-based moving objects detection for intelligent automobiles and a robustness enhancing method. ICCE-TW 2014: 75-76 - [c78]Jui-Sheng Lee, Hsiu-Cheng Chang, Jiun-In Guo:
An Adaboost-based two-level moving object detection architecture with dynamic ROI allocation. ICCE-TW 2014: 103-104 - [c77]Guan-Yu Chen, Po-Chun Shen, Chao-Yi Cho, M. S. Vinay, Jiun-In Guo:
A forward collision avoidance system adopting multi-feature vehicle detection. ICCE-TW 2014: 125-126 - [c76]Kai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A 360-degree panoramic video system design. VLSI-DAT 2014: 1-4 - 2013
- [j24]Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo:
Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization. J. Signal Process. Syst. 72(1): 17-33 (2013) - [c75]Yuan-Hsiang Miao, Guo-An Jian, Li-Ching Wang, Jui-Sheng Lee, Jiun-In Guo:
A low complexity multi-view video encoder exploiting B-frame characteristics. APSIPA 2013: 1-4 - [c74]Ching-Hwa Cheng, Sheng-Wei Hsu, Jiun-In Guo:
A low-cost scalable Voltage-Frequency Adjustor for implementing low-power systems. ISCAS 2013: 655-658 - [c73]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159 - [c72]Guo-An Jian, Jui-Sheng Lee, Kheng-Joo Tan, Peng-Sheng Chen, Jiun-In Guo:
A real-time parallel scalable video encoder for multimedia streaming systems. VLSI-DAT 2013: 1-4 - [c71]Jui-Sheng Lee, Yuan-Hsiang Miao, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A view scalable multi-view video decoder system. VLSI-DAT 2013: 1-4 - 2012
- [j23]Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo:
A Verification-Aware Design Methodology for Thread Pipelining Parallelization. IEICE Trans. Inf. Syst. 95-D(10): 2505-2513 (2012) - [j22]Cheng-An Chien, Guo-An Jian, Hsiu-Cheng Chang, Kuan-Hung Chen, Jiun-In Guo:
High efficiency data access system architecture for deblocking filter supporting multiple video coding standards. IEEE Trans. Consumer Electron. 58(2): 670-678 (2012) - [c70]Jui-Sheng Lee, Sheng-Han Wang, Chih-Tai Chou, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
An inter-frame/inter-view cache architecture design for multi-view video decoders. APSIPA 2012: 1-4 - [c69]Cheng-Yen Chang, Cheng-An Chien, Hsiu-Cheng Chang, Jia-Wei Chen, Jiun-In Guo:
A two level mode decision algorithm for H.264 high profile intra encoding. ISCAS 2012: 508-511 - [c68]Jui-Sheng Lee, Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo:
3D depth map generation for embedded stereo applications. VCIP 2012: 1-6 - [c67]Ching-Hwa Cheng, Jiun-In Guo:
A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism. VLSI-DAT 2012: 1-4 - [c66]Sheng-Wei Fan, Jia-Wai Chen, Jiun-In Guo:
Low bandwidth HD1080@60FPS JPEG-XR transform design. VLSI-DAT 2012: 1-4 - 2011
- [j21]Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, Jiun-In Guo:
Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 183-192 (2011) - [j20]Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, Jiun-In Guo:
A dynamic quality-adjustable H.264 intra coder. IEEE Trans. Consumer Electron. 57(3): 1203-1211 (2011) - [c65]Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng:
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC 2011: 73-74 - [c64]Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo:
Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. ASP-DAC 2011: 85-86 - [c63]Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo:
A low-power management technique for high-performance domino circuits. ASP-DAC 2011: 93-94 - 2010
- [j19]Ke Xu, Tsu-Ming Liu, Jiun-In Guo, Oliver Chiu-sing Choy:
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding. J. Signal Process. Syst. 60(1): 131-145 (2010) - [c62]Bing-Tsung Wu, Jiun-In Guo:
Low compute complexity BU-based rate control algorithm for H.264/AVC encoder. APCCAS 2010: 564-567 - [c61]Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo:
Dynamic voltage domain assignment technique for low power performance manageable cell based design. ASP-DAC 2010: 359-360 - [c60]Chih-Chuan Yang, Kheng-Joo Tan, Yao-Chang Yang, Jiun-In Guo:
Low complexity fractional motion estimation with adaptive mode selection for H.264/AVC. ICME 2010: 673-678 - [c59]Kheng-Joo Tan, Jia-Wei Gong, Bing-Tsung Wu, Dou-Cheng Chang, Hsin-Yi Li, Yi-Mao Hsiao, Yung-Chung Chen, Shi-Wu Lo, Yuan-Sun Chu, Jiun-In Guo:
A remote thin client system for real time multimedia streaming over VNC. ICME 2010: 992-997 - [c58]Chang-Hung Tsai, Kheng-Joo Tan, Ching-Lung Su, Jiun-In Guo:
A group of macroblock based motion estimation algorithm supporting adaptive search range for H.264 video coding. ISCAS 2010: 1891-1894
2000 – 2009
- 2009
- [j18]Yao-Chang Yang, Jiun-In Guo:
High-Throughput H.264/AVC High-Profile CABAC Decoder for HDTV Applications. IEEE Trans. Circuits Syst. Video Technol. 19(9): 1395-1399 (2009) - [j17]Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, Jinn-Shyan Wang:
VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism. IEEE Trans. Circuits Syst. Video Technol. 19(11): 1633-1645 (2009) - [j16]Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, Jiun-In Guo:
A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications. IEEE Trans. Circuits Syst. Video Technol. 19(12): 1739-1754 (2009) - [j15]Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. ACM Trans. Design Autom. Electr. Syst. 14(1): 17:1-17:17 (2009) - [c57]Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo:
CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. ASP-DAC 2009: 93-94 - [c56]Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang:
A dynamic quality-scalable H.264 video encoder chip. ASP-DAC 2009: 125-126 - [c55]Guo-An Jian, Jui-Chin Chu, Jiun-In Guo:
Optimization of AVS-M Video Decoder for Real-time Implementation on Embedded RISC Processors. IIH-MSP 2009: 98-101 - [c54]Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo:
A Dynamic Quality-scalable H.264 Video Encoder. ISCAS 2009: 1932 - [c53]Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A Multi-standard Video Decoder for High Definition Video Applications. ISCAS 2009: 1933 - [c52]Guo-An Jian, Jui-Chin Chu, Ting-Yu Huang, Tao-Cheng Chang, Jiun-In Guo:
A System Architecture Exploration on the Configurable HW/SW Co-design for H.264 Video Decoder. ISCAS 2009: 2237-2240 - [c51]Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards. ISCAS 2009: 2377-2380 - [c50]Tao-Cheng Chang, Hung-Wei Shen, Jiun-In Guo:
A Low Complexity Error Concealment Method for H.264 Video Coding Facilitating Hardware Realization. ISPAN 2009: 470-473 - [c49]Guo-An Jian, Ting-Yu Huang, Jui-Chin Chu, Jiun-In Guo:
Optimization of VC-1/H.264/AVS Video Decoders on Embedded Processors. ITNG 2009: 1313-1318 - 2008
- [c48]Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding. APCCAS 2008: 312-315 - [c47]Bing-Tsung Wu, Tzu-Chun Chang, Jiun-In Guo, Ching-Lung Su:
A novel basic unit level rate control algorithm and architecture for H.264/AVC video encoders. APCCAS 2008: 1300-1303 - [c46]Ping-Tsung Wu, Tzu-Chun Chang, Ching-Lung Su, Jiun-In Guo:
A H.264 basic-unit level rate control algorithm facilitating hardware realization. ICASSP 2008: 2185-2188 - [c45]Ting-Yu Huang, Guo-An Jian, Jui-Chin Chu, Ching-Lung Su, Jiun-In Guo:
Joint algorithm/code-level optimization of H.264 video decoder for mobile multimedia applications. ICASSP 2008: 2189-2192 - 2007
- [j14]Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang, Ming-Chih Tsai, Jiun-In Guo, Jinn-Shyan Wang:
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. IEEE J. Solid State Circuits 42(1): 170-182 (2007) - [c44]Jui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, Jiun-In Guo:
An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model. DAC 2007: 652-657 - [c43]Guo-An Jian, Jiun-In Guo:
Low Complexity Multi-Standard Video Player for Portable Multimedia Applications. ICME 2007: 7 - [c42]Chih-Da Chien, Chih-Wei Wang, Chiun-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, Jiun-In Guo:
A Low Latency Memory Controller for Video Coding Systems. ICME 2007: 1211-1214 - [c41]Guo-An Jian, Chih-Da Chien, Jiun-In Guo:
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. ISCAS 2007: 1569-1572 - [c40]Kuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, Jiun-In Guo:
A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique. ISCAS 2007: 3139-3142 - [c39]Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shyan Wang, Jiun-In Guo:
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. ISSCC 2007: 280-603 - [c38]Chih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, Jiun-In Guo:
A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications. ISSCC 2007: 282-603 - [c37]Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo:
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. SiPS 2007: 521-526 - 2006
- [j13]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang:
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264. IEEE Trans. Circuits Syst. Video Technol. 16(4): 472-483 (2006) - [j12]Chih-Da Chien, Keng-Po Lu, Yu-Min Chen, Jiun-In Guo, Yuan-Sun Chu, Ching-Lung Su:
An Area-Efficient Variable Length Decoder IP Core Design for MPEG-1/2/4 Video Coding Applications. IEEE Trans. Circuits Syst. Video Technol. 16(9): 1172-1178 (2006) - [c36]Ching-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao-Chang Yang, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng:
A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC. APCCAS 2006: 398-401 - [c35]Ching-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao Li, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng:
Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC. APCCAS 2006: 578-581 - [c34]Ming-Shuan Lee, Jui-Chin Chu, Jiun-In Guo:
Predictive Mode Searching Policy for H.264/AVC Intra Prediction. APCCAS 2006: 764-767 - [c33]Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang:
Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application. ICASSP (3) 2006: 932-935 - [c32]Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-Heng Kang, Tien-Fu Chen, Jiun-In Guo:
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications. ICME 2006: 25-28 - [c31]Yao-Chang Yang, Chien-Chang Lin, Hsui-Cheng Chang, Ching-Lung Su, Jiun-In Guo:
A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing. ICME 2006: 357-360 - [c30]Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang:
A Condition-based Intra Prediction Algorithm for H.264/AVC. ICME 2006: 1077-1080 - [c29]Kuo-Chuan Chao, Kuan-Hung Chen, Yuan-Sun Chu, Jiun-In Guo:
Low-power mechanism with power block management. ISCAS 2006 - [c28]Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo:
A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. ISCAS 2006 - [c27]Chih-Da Chien, Keng-Po Lu, Yi-Hung Shih, Jiun-In Guo:
A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications. ISCAS 2006 - [c26]Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen:
Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications. ISCAS 2006 - 2005
- [j11]Hun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, Chein-Wei Jen:
The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning. IEICE Trans. Electron. 88-C(5): 1061-1069 (2005) - [j10]Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen:
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. IEEE Trans. Circuits Syst. Video Technol. 15(3): 445-453 (2005) - [j9]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen:
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. IEEE Trans. Circuits Syst. Video Technol. 15(5): 704-715 (2005) - [c25]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang:
An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. ISCAS (5) 2005: 4517-4520 - [c24]Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, Jiun-In Guo:
A low-power motion compensation IP core design for MPEG-1/2/4 video decoding. ISCAS (5) 2005: 4542-4545 - [c23]Hsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo:
A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. ISCAS (6) 2005: 6110-6113 - [c22]Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo:
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. ISLPED 2005: 155-160 - 2004
- [j8]Jiun-In Guo, Rei-Chin Ju, Jia-Wei Chen:
An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization. IEEE Trans. Circuits Syst. Video Technol. 14(4): 416-428 (2004) - [c21]Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo:
A high-performance MPEG4 bitstream processing core. ICME 2004: 467-470 - [c20]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh:
A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. ICME 2004: 1683-1686 - [c19]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen:
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. ISCAS (2) 2004: 141-144 - [c18]Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen:
A power-aware IP core generator for the one-dimensional discrete Fourier transform. ISCAS (3) 2004: 637-640 - [c17]Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen:
A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. ISCAS (2) 2004: 769-772 - 2003
- [j7]Hun-Chen Chen, Jiun-In Guo, Lin-Chieh Huang, Jui-Cheng Yen:
Design and Realization of a New Signal Security System for Multimedia Data Transmission. EURASIP J. Adv. Signal Process. 2003(13): 1291-1305 (2003) - [j6]Jiun-In Guo, Jui-Cheng Yen:
An Efficient IDCT Processor Design for HDTV Applications. J. VLSI Signal Process. 33(1-2): 147-155 (2003) - [c16]Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen:
A memory efficient realization of cyclic convolution and its application to discrete cosine transform. ISCAS (4) 2003: 33-36 - [c15]Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin:
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. ISCAS (5) 2003: 293-296 - [c14]Jiun-In Guo, Jia-Wei Chen, Han-Chen Chen:
A new 2-D 8×8 DCT/IDT core design using group distributed arithmetic. ISCAS (2) 2003: 752-755 - 2002
- [j5]Jiun-In Guo, Chien-Chang Lin, Chih-Da Chien:
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths. J. Circuits Syst. Comput. 11(4): 405-428 (2002) - [c13]Jui-Cheng Yen, Jiun-In Guo:
Design of a new signal security system. ISCAS (4) 2002: 121-124 - [c12]Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen:
A new group distributed arithmetic design for the one dimensional discrete Fourier transform. ISCAS (1) 2002: 421-424 - [c11]Jiun-In Guo, Chien-Chang Lin:
A new hardware efficient design for the one dimensional discrete Fourier transform. ISCAS (5) 2002: 549-552 - [c10]Hun-Chen Chen, Jui-Cheng Yen, Jiun-In Guo:
Design of a New Cryptography System. IEEE Pacific Rim Conference on Multimedia 2002: 1041-1048 - 2001
- [j4]Jiun-In Guo, Chih-Chen Li:
A generalized architecture for the one-dimensional discrete cosine and sine transforms. IEEE Trans. Circuits Syst. Video Technol. 11(7): 874-881 (2001) - [c9]Jiun-In Guo:
A low cost 2-D inverse discrete cosine transform design for image compression. ISCAS (4) 2001: 658-661 - [c8]Jiun-In Guo:
A new DA-based array for one dimensional discrete Hartley transform. ISCAS (4) 2001: 662-665 - 2000
- [j3]Jiun-In Guo:
An efficient design for one-dimensional discrete Hartley transform using parallel additions. IEEE Trans. Signal Process. 48(10): 2806-2813 (2000) - [c7]Jui-Cheng Yen, Jiun-In Guo:
A new chaotic key-based design for image encryption and decryption. ISCAS 2000: 49-52 - [c6]Jiun-In Guo:
An efficient design for one dimensional discrete cosine transform using parallel adders. ISCAS 2000: 725-728
1990 – 1999
- 1998
- [j2]Jui-Cheng Yen, Jiun-In Guo, Hun-Chen Chen:
A new k-winners-take-all neural network and its array architecture. IEEE Trans. Neural Networks 9(5): 901-912 (1998) - 1994
- [c5]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A novel VLSI array design for the discrete Hartley transform using cyclic convolution. ICASSP (2) 1994: 501-504 - [c4]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. ISCAS 1994: 235-238 - 1993
- [j1]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A New Array Architecture for Prime-Length Discrete Cosine Transform. IEEE Trans. Signal Process. 41(1): 436-441 (1993) - [c3]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. ISCAS 1993: 1571-1574 - [c2]Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen:
A Multi-phase Shared Bus Structure for the Fast Fourier Transform. ISCAS 1993: 1575-1578 - 1992
- [c1]Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A memory-based approach to design and implement systolic arrays for DFT and DCT. ICASSP 1992: 621-624
Coauthor Index
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