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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15
Volume 15, Number 1, January 2007
- Zhengtao Yu, Xun Liu:
Low-Power Rotary Clock Array Design. 5-12 - Yen-Jen Chang, Maofeng Lan:
Two New Techniques Integrated for Energy-Efficient TLB Design. 13-23 - Pallav Gupta, Niraj K. Jha, Loganathan Lingappan:
A Test Generation Framework for Quantum Cellular Automata Circuits. 24-36 - Erkan Acar, Sule Ozev:
Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup. 37-47 - Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. 48-59 - Dipanjan Gope, Albert E. Ruehli, Vikram Jandhyala:
Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm. 60-68 - Ruibing Lu, Aiqun Cao, Cheng-Kok Koh:
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. 69-79 - Afshin Abdollahi, Farzan Fallah, Massoud Pedram:
A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design. 80-89 - Ye Li, Bertan Bakkaloglu
, Chaitali Chakrabarti:
A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends. 90-103 - Zhongfeng Wang, Zhiqiang Cui:
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. 104-114 - K. Scott Hemmert, Keith D. Underwood:
Floating-Point Divider Design for FPGAs. 115-118 - P. Rajesh Kumar, K. Sridharan:
VLSI-Efficient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment. 118-123
Volume 15, Number 2, February 2007
- Amir Amirabadi, Ali Afzali-Kusha, Y. Mortazavi, Mehrdad Nourani:
Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper. 125-134 - Jonathan Rosenfeld, Eby G. Friedman:
Design Methodology for Global Resonant H-Tree Clock Distribution Networks. 135-148 - Ganesh Venkataraman, Jiang Hu, Frank Liu:
Integrated Placement and Skew Optimization for Rotary Clocking. 149-158 - Zhijian Lu, Wei Huang, Mircea R. Stan, Kevin Skadron, John C. Lach:
Interconnect Lifetime Prediction for Reliability-Aware Systems. 159-172 - Richard F. Hobson:
A New Single-Ended SRAM Cell With Write-Assist. 173-181 - Jason Meyer, Fatih Kocan:
Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. 182-195 - Mohammad Sharifkhani, Manoj Sachdev:
Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. 196-205 - Vishal Khandelwal, Ankur Srivastava:
A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. 206-215 - John Marty Emmert, Charles E. Stroud, Miron Abramovici:
Online Fault Tolerance for FPGA Logic Blocks. 216-226 - Hae-Moon Seo, YeonKug Moon, Yong-Kuk Park, Dongsu Kim, Dong-Sun Kim, Youn-Sung Lee, Kwang-Ho Won, Seong-Dong Kim, Pyung Choi:
A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks. 227-231 - Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. 231-236 - Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee:
Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. 236-240 - Sankalp S. Kallakuri, Alex Doboli:
Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes. 240-245
Volume 15, Number 3, March 2007
- Niraj K. Jha:
Editorial. 249-261 - Alexandru Andrei, Petru Eles, Zebo Peng, Marcus T. Schmitz, Bashir M. Al-Hashimi:
Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. 262-275 - Nikhil Jayakumar, Sunil P. Khatri:
A Predictably Low-Leakage ASIC Design Style. 276-285 - Abbes Amira, Shrutisagar Chandrasekaran:
Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing. 286-295 - Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. 296-308 - Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak:
Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding. 309-318 - Ada S. Y. Poon:
An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications. 319-327 - Sizhong Chen, Tong Zhang, Yan Xin:
Relaxed K-Best MIMO Signal Detector Design and VLSI Implementation. 328-337 - Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang:
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop. 338-345 - Chen Shoushun, Amine Bermak:
Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization. 346-357 - Wei-Zen Chen, Da-Shin Lin:
A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology. 358-365 - Justin Gregg, Tom W. Chen:
Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing. 366-376
Volume 15, Number 4, April 2007
- Lesley Shannon, Paul Chow:
SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. 377-390 - Tajana Simunic Rosing, Kresimir Mihic, Giovanni De Micheli:
Power and Reliability Management of SoCs. 391-403 - Xiaoding Chen, Michael S. Hsiao:
An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. 404-412 - Siavash Bayat Sarmadi, M. Anwar Hasan:
On Concurrent Detection of Errors in Polynomial Basis Multiplication. 413-426 - Jiong Luo, Niraj K. Jha, Li-Shiuan Peh:
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. 427-437 - Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
Optimal Positions of Twists in Global On-Chip Differential Interconnects. 438-446 - Florin Balasa, Hongwei Zhu, Ilie I. Luican:
Computation of Storage Requirements for Multi-Dimensional Signal Processing Applications. 447-460 - Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou:
Testable Designs of Multiple Precharged Domino Circuits. 461-465 - Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee:
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. 465-470 - Zhongfeng Wang:
High-Speed Recursion Architectures for MAP-Based Turbo Decoders. 470-474 - Dong-U Lee, Ray C. C. Cheung, John D. Villasenor:
A Flexible Architecture for Precise Gamma Correction. 474-478 - Brandon J. Jasionowski, Michelle K. Lay, Martin Margala:
A Processor-In-Memory Architecture for Multimedia Compression. 478-483 - Zhongfeng Wang, Zhiqiang Cui:
A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. 483-488 - Dimitrios Kagaris, Themistoklis Haniotakis:
A Methodology for Transistor-Efficient Supergate Design. 488-492
Volume 15, Number 5, May 2007
- Dimitris Gizopoulos, Robert C. Aitken, Sandip Kundu:
Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems". 493-494 - Todd J. Foster, Dennis L. Lastor, Padmaraj Singh:
First Silicon Functional Validation and Debug of Multicore Microprocessors. 495-504 - Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao:
Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. 505-517 - Loganathan Lingappan, Niraj K. Jha:
Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. 518-530 - Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra:
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. 531-540 - Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu:
STEAC: A Platform for Automatic SOC Test Integration. 541-545 - Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Architectural Support for Run-Time Validation of Program Data Properties. 546-559 - Mohamed Elgebaly, Manoj Sachdev:
Variation-Aware Adaptive Voltage Scaling System. 560-571 - Antonio Zenteno Ramírez, Guillermo Espinosa, Víctor H. Champac:
Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. 572-577 - Encarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz:
IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. 578-591 - Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail:
Thermal Management of On-Chip Caches Through Power Density Minimization. 592-604 - Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha:
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. 605-609
Volume 15, Number 6, June 2007
- Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown:
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. 613-623 - Tianpei Zhang, Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. 624-636 - Jun Cheng Chi, Hung Hsie Lee, Sung Han Tsai, Mely Chen Chi:
Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint. 637-648 - Hiroshi Yamamoto, Jeffrey A. Davis:
Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. 649-659 - Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy:
Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. 660-671 - Scott C. Smith:
Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. 672-683 - Montek Singh, Steven M. Nowick:
MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. 684-698 - Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. 699-710 - Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos:
Sorter Based Permutation Units for Media-Enhanced Microprocessors. 711-715 - Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. 716-720 - Delong Shang, Alexandre Yakovlev, Albert Koelmans, Danil Sokolov, Alexandre V. Bystrov:
Registers for Phase Difference Based Logic. 720-724 - Shih-Chang Hsia, Szu-Hong Wang:
Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. 725-728
Volume 15, Number 7, July 2007
- Ka-Ming Keung, Vineela Manne, Akhilesh Tyagi:
A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. 733-745 - Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm:
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. 746-757 - Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi:
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. 758-766 - Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. 767-776 - Seongmoon Wang:
A BIST TPG for Low Power Dissipation and High Fault Coverage. 777-789 - Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. 790-800 - Myoung-Cheol Shin, In-Cheol Park:
SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. 801-810 - Xinmiao Zhang:
Further Exploring the Strength of Prediction in the Factorization of Soft-Decision Reed-Solomon Decoding. 811-820 - Tony Tae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim:
Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. 821-829 - Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He:
Microarchitecture Configurations and Floorplanning Co-Optimization. 830-841 - Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Concurrent Error Detection in Reed-Solomon Encoders and Decoders. 842-846 - Kuan-Hung Chen, Yuan-Sun Chu:
A Low-Power Multiplier With the Spurious Power Suppression Technique. 846-850
Volume 15, Number 8, August 2007
- Guest Editorial System-Level Interconnect Prediction. 853-854
- Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh:
Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks. 855-868 - Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo:
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. 869-880 - Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang:
Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. 881-894 - Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown:
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. 895-903 - Andrew B. Kahng, Bao Liu, Qinke Wang:
Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. 904-912 - Xiaoji Ye, Frank Liu, Peng Li:
Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. 913-926 - Ian O'Connor, Faress Tissafi-Drissi, Frédéric Gaffiot, Joni Dambre, Michiel De Wilde, Jan Van Campenhout, Dries Van Thourhout, Dirk Stroobandt:
Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect. 927-940 - Jin Guo, Antonis Papanikolaou, H. Zhang, Francky Catthoor:
Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture. 941-944 - Wenyi Feng, Jonathan W. Greene:
Post-Placement Interconnect Entropy. 945-948 - Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow:
Routability of Network Topologies in FPGAs. 948-951 - Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor:
Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. 952-962 - Ja Chun Ku, Yehea I. Ismail:
Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. 963-970 - Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis:
Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. 971-975 - Yuan Xie, Wayne H. Wolf, Haris Lekatsas:
Code Decompression Unit Design for VLIW Embedded Processors. 975-980
Volume 15, Number 9, September 2007
- N. Gupta:
A VLSI Architecture for Image Registration in Real Time. 981-989 - Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis:
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. 990-1002 - N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
Run-Time Integration of Reconfigurable Video Processing Systems. 1003-1016 - Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, Chih-Kong Ken Yang:
Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. 1017-1027 - David Kinniment, Charles E. Dike, Keith Heron, Gordon Russell, Alexandre Yakovlev:
Measuring Deep Metastability and Its Effect on Synchronizer Performance. 1028-1039 - Seraj Ahmad, Rabi N. Mahapatra:
An Efficient Approach to On-Chip Logic Minimization. 1040-1050 - Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Bryan S. Goda, John F. McDonald:
A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. 1051-1054 - Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima:
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. 1055-1059 - Seongmoo Heo, Ronny Krashinsky, Krste Asanovic:
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. 1060-1064
Volume 15, Number 10, October 2007
- Radu M. Secareanu, Andrew Marshall:
Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications. 1065-1066 - Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li:
Utilizing Redundancy for Timing Critical Interconnect. 1067-1080 - Vasilis F. Pavlidis, Eby G. Friedman:
3-D Topologies for Networks-on-Chip. 1081-1090 - Xin Wang, Tapani Ahonen, Jari Nurmi:
Applying CDMA Technique to Network-on-Chip. 1091-1100 - Koichiro Noguchi, Makoto Nagata:
An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. 1101-1110 - Sujan Pandey, Manfred Glesner:
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. 1111-1124 - Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas:
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. 1125-1134 - Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng:
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. 1135-1143 - Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Wafer-Level Modular Testing of Core-Based SoCs. 1144-1154 - Venkat Satagopan, Bonita Bhaskaran, Waleed K. Al-Assadi, Scott C. Smith, Sindhu Kakarla:
DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. 1155-1159 - Chang Hong Lin, Yuan Xie, Wayne H. Wolf:
Code Compression for VLIW Embedded Systems Using a Self-Generating Table. 1160-1171 - Jie Jin, Chi-Ying Tsui:
Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. 1172-1176
Volume 15, Number 11, November 2007
- Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee:
An Overview of a Compiler for Mapping Software Binaries to Hardware. 1177-1190 - Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. 1191-1204 - Peng Li, Zhuo Feng, Emrah Acar:
Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. 1205-1214 - Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka:
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. 1215-1224 - Jun Ma, Alexander Vardy, Zhongfeng Wang:
Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. 1225-1238 - Atul Maheshwari, Wayne P. Burleson:
Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. 1239-1244 - Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal:
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. 1245-1255 - Montek Singh, Steven M. Nowick:
The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. 1256-1269 - Montek Singh, Steven M. Nowick:
The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style. 1270-1283 - Bao Liu, Sheldon X.-D. Tan:
Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs. 1284-1287
Volume 15, Number 12, December 2007
- Qinwei Xu, Pinaki Mazumder:
Efficient Modeling of Transmission Lines With Electromagnetic Wave Coupling by Using the Finite Difference Quadrature Method. 1289-1302 - Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang:
Optimization of Pattern Matching Circuits for Regular Expression on FPGA. 1303-1310 - Zhiyu Liu, Volkan Kursun:
PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. 1311-1319 - Hossein Asadi, Mehdi Baradaran Tahoori:
Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs. 1320-1331 - Ke Cao, Jiang Hu, Mosong Cheng:
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. 1332-1340 - Hao-Chiao Hong:
A Design-for-Digital-Testability Circuit Structure for Sigma-Delta Modulators. 1341-1350 - Yung-Chuan Jiang, Jhing-Fa Wang:
Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing. 1351-1361 - Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis:
Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System. 1362-1366
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