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ORCIDISSCC 2013: San Francisco, CA, USA
- 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013. IEEE 2013, ISBN 978-1-4673-4515-6
- Laura Chizuko Fujino:
Welcome! 1 - Laura Chizuko Fujino:
Reflections. 4 - Anantha P. Chandrakasan, Bram Nauta:
Session 1 overview: Plenary session. 6-7 - Lisa T. Su:
"Architecting the future through heterogeneous computing". 8-11 - Yoshiyuki Miyabe:
"Smart life solutions" from home to city. 12-17 - Martin van den Brink:
Continuing to shrink: Next-generation lithography - Progress and prospects. 20-25 - Carver Mead:
The evolution of technology. 26 - Ken Chang, Hisakatsu Yamaguchi:
Session 2 overview: Ultra-high-speed transceivers and equalizers. 26-27 - Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada:
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. 28-29 - Yue Lu, Elad Alon:
A 66Gb/s 46mW 3-tap decision-feedback equalizer in 65nm CMOS. 30-31 - Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS. 32-33 - Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz:
A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS. 34-35 - Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. 36-37 - Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang:
A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS. 38-39 - Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura:
32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE. 40-41 - Kwangmo Jung, Amir Amirkhany, Kambiz Kaviani:
A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS. 42-43 - Se-Hyun Yang, Eric Fluhr:
Session 3 overview: Processors. 44-45 - James D. Warnock, Yuen H. Chan, Hubert Harrer, David L. Rude, Ruchir Puri, Sean M. Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, Adam Jatkowski, Gerald Strevig, Leon J. Sigal, Ayan Datta, Anne Gattiker, Aditya Bansal, Doug Malone, Thomas Strach, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb:
5.5GHz system z microprocessor and multi-chip module. 46-47 - Jason Hart, Steve Butler, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Lance Kwong, Robert P. Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen:
3.6GHz 16-core SPARC SoC processor in 28nm. 48-49 - Jen-Wei Lee, Szu-Chi Chung
, Hsie-Chia Chang, Chen-Yi Lee:
Processor with side-channel attack resistance. 50-51 - Teja Singh, Joshua Bell, Shane Southard:
Jaguar: A next-generation low-power x86-64 core. 52-53 - Weiwu Hu, Yifu Zhang, Liang Yang, Bao-Xia Fan, Yunji Chen, Shi-Qiang Zhong, Huandong Wang, Zichu Qi, Pengyu Wang, Xiang Gao, Xu Yang, Bin Xiao, Hongsheng Wang, Zongren Yang, Liqiong Yang, Shuai Chen:
Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor. 54-55 - Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu:
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. 56-57 - Venkatram Krishnaswamy, Dawei Huang, Sebastian Turullols, Jinuk Luke Shin:
Bandwidth and power management of glueless 8-socket SPARC T5 system. 58-59 - Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Ryuichi Nishiyama, Sota Sakabayashi, Yoichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada:
A 10th generation 16-core SPARC64 processor for mission-critical UNIX server. 60-61 - Jae-Youl Lee, Saska Lindfors:
Session 4 overview: Harvesting & wireless power. 62-63 - Jun-Han Choi, Sung-Ku Yeo, Chang-Byong Park, Seho Park, Jeong Seok Lee, Gyu-Hyeong Cho:
A resonant regulating rectifier (3R) operating at 6.78 MHz for a 6W wireless charger with 86% efficiency. 64-65 - Yan Lu, Xing Li, Wing-Hung Ki, Chi-Ying Tsui, C. Patrick Yue:
A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices. 66-67 - Kin Wai Roy Chew, Zhuochao Sun, Howard Tang, Liter Siek:
A 400nW single-inductor dual-input-tri-output DC-DC buck-boost converter with maximum power point tracking for indoor photovoltaic energy harvesting. 68-69 - Wen-Chuen Liu, Yi-Hsiang Wang, Tai-Haur Kuo:
An adaptive load-line tuning IC for photovoltaic module integrated mobile device with 470µs transient time, over 99% steady-state accuracy and 94% power conversion efficiency. 70-71 - Tsung-Heng Tsai, Kai Chen:
A 3.4mW photovoltaic energy-harvesting charger with integrated maximum power point tracking and battery management. 72-73 - Stefano Stanzione, Chris van Liempd, Rob van Schaijk, Yasuyuki Naito, Refet Firat Yazicioglu, Chris Van Hoof:
A self-biased 5-to-60V input voltage and 25-to-1600µW integrated DC-DC buck converter with fully analog MPPT algorithm reaching up to 88% end-to-end efficiency. 74-75 - Chris van Liempd, Stefano Stanzione, Younis Allasasmeh, Chris Van Hoof:
A 1µW-to-1mW energy-aware interface IC for piezoelectric harvesting with 40nA quiescent current and zero-bias active rectifiers. 76-77 - Dongwon Kwon, Gabriel A. Rincón-Mora:
A single-inductor 0.35µm CMOS energy-investing piezoelectric harvester. 78-79 - Mike Keaveney, Joe Golat:
Session 5 overview: RF techniques. 80-81 - Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello:
SAW-less analog front-end receivers for TDD and FDD. 82-83 - Amir Ghaffari, Eric A. M. Klumperink, Frank E. van Vliet, Bram Nauta:
Simultaneous spatial and frequency-domain filtering at the antenna inputs achieving up to +10dBm out-of-band/beam P1dB. 84-85 - Mohyee Mikhemar, David Murphy, Ahmad Mirzaei, Hooman Darabi:
A phase-noise and spur filtering technique using reciprocal-mixing cancellation. 86-87 - Maryam Fathi, David K. Su, Bruce A. Wooley:
A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifier. 88-89 - Kohei Onizuka, Shigehito Saigusa, Shoji Otaka:
A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications. 90-91 - Sang-Sung Lee, Jaeheon Lee, In-Young Lee, Sang-Gug Lee, Jinho Ko:
A new TX leakage-suppression technique for an RFID receiver using a dead-zone amplifier. 92-93 - Frederic Roger:
A 200mW 100MHz-to-4GHz 11th-order complex analog memory polynomial predistorter for wireless infrastructure RF amplifiers. 94-95 - David Ruffieux, Yogesh K. Ramadass:
Session 6 overview: Emerging medical and sensor technologies technology directions subcommittee. 96-97 - Kiseok Song, Unsoo Ha, Jaehyuk Lee, Kyeongryeol Bong, Hoi-Jun Yoo:
An 87mA·min iontophoresis controller IC with dual-mode impedance sensor for patch-type transdermal drug delivery system. 98-99 - Muhammad Awais Bin Altaf, Judyta Tillak, Yonatan Kifle, Jerald Yoo:
A 1.83µJ/classification nonlinear support-vector-machine-based patient-specific seizure classification SoC. 100-101 - Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong:
Through-silicon-via-based double-side integrated microsystem for neural sensing applications. 102-103 - Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. 104-105 - Sahel Abdinia, Mohamed Benwadih, Romain Coppard, Stéphanie Jacob, Giorgio Maiellaro, Giuseppe Palmisano, Mariantonietta Rizzo, Antonino Scuderi, Francesca Tramontana, Arthur H. M. van Roermund, Eugenio Cantatore:
A 4b ADC manufactured in a fully-printed organic complementary technology including resistors. 106-107 - Daniele Raiteri, Pieter van Lieshout, Arthur H. M. van Roermund, Eugenio Cantatore:
An organic VCO-based ADC for quasi-static signals achieving 1LSB INL at 6b resolution. 108-109 - Yuki Maruyama, Jordana Blacksberg, Edoardo Charbon:
A 1024×8 700ps time-gated SPAD line sensor for laser raman spectroscopy and LIBS in space and rover-based planetary exploration. 110-111 - Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs. 112-113 - Ichiro Fujimori, Masafumi Nogawa:
Session 7 overview: Optical transceivers and silicon photonics. 114-115 - Georgios Kalogerakis, Tim Moran, Thelinh Nguyen, Gilles Denoyer:
A quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB crosstalk penalty. 116-117 - Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka:
A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects. 118-119 - Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee:
100Gb/s ethernet chipsets in 65nm CMOS technology. 120-121 - Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
A blind baud-rate ADC-based CDR. 122-123 - Cheng Li, Rui Bai, Ayman Shafik, Ehsan Zhian Tabasy, Geng Tang, Chao Ma, Chin-Hui Chen, Zhen Peng, Marco Fiorentino, Patrick Chiang, Samuel Palermo:
A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver. 124-125 - Benjamin Moss, Chen Sun, Michael Georgas, Jeffrey Shainline, Jason Orcutt, Jonathan C. Leu, Mark T. Wade, Yu-Hsin Chen, Kareem Nammari, Xiaoxi Wang, Hanqing Li, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic:
A 1.23pJ/b 2.5Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOI. 126-127 - Xiaotie Wu, Bipin Dama, Prakash Gothoskar, Peter Metz, Kal Shastri, Sanjay Sunder, Jan Van der Spiegel, Yifan Wang, Mark Webster, Will Wilson:
A 20Gb/s NRZ/PAM-4 1V transmitter in 40nm CMOS driving a Si-photonic modulator in 0.13µm CMOS. 128-129 - Jonathan E. Proesel, Alexander V. Rylyakov, Clint Schow:
Optical receivers using DFE-IIR equalization. 130-131 - Yi Zhao, Leonardo Vera, John R. Long, David L. Harame:
A 10Gb/s 6Vpp differential modulator driver in 0.18µm SiGe-BiCMOS. 132-133 - Ullrich R. Pfeiffer, Gabriel M. Rebeiz:
Session 8 overview: Millimeter-wave techniques. 134-135 - Zheng Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, Payam Heydari:
A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS. 136-137 - Ruonan Han, Ehsan Afshari:
A 260GHz broadband source with 1.1mW continuous-wave radiated power and EIRP of 15.7dBm in 65nm CMOS. 138-139 - Omeed Momeni:
A 260GHz amplifier with 9.2dB gain and -3.9dBm saturated power in 65nm CMOS. 140-141 - Wei Tai, L. Richard Carley, David S. Ricketts:
A 0.7W fully integrated 42GHz power amplifier with 10% PAE in 0.13µm SiGe BiCMOS. 142-143 - Francis Caster, Leland Gilreath, Shiji Pan, Zheng Wang, Filippo Capolino, Payam Heydari:
A 93-to-113GHz BiCMOS 9-element imaging array receiver utilizing spatial-overlapping pixels with wideband phase and amplitude control. 144-145 - Pang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee:
A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS. 146-147 - Yaoming Sun, Miroslav Marinkovic, Gunter Fischer, Wolfgang Winkler, Wojciech Debski, Stefan Beer, Thomas Zwick, Mekdes G. Girma, Jürgen Hasch, Christoph Scheytt:
A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization. 148-149 - Qiyang Wu, Tony Quach, Aji Mattamana, Salma Elabd, Steven R. Dooley, Jamin J. McCue, Pompei L. Orlando, Gregory L. Creech, Waleed Khalil:
A 10mW 37.8GHz current-redistribution BiCMOS VCO with an average FOMT of -193.5dBc/Hz. 150-151 - Michael Polley, Yongha Park:
Session 9 overview: Mobile application processors and media accelerators. 152-153 - Youngmin Shin, Ken Shin, Prashant Kenkare, Rajesh Kashyap, Hoi-Jin Lee, Dongjoo Seo, Brian Millar, Yohan Kwon, Ravi Iyengar, Min-Su Kim, Ahsan Chowdhury, Sung-il Bae, Inpyo Hong, Wookyeong Jeong, Aaron Lindner, Ukrae Cho, Keith Hawkins, Jae-Cheol Son, Seung Ho Hwang:
28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor. 154-155 - Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor. 156-157 - Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. 158-159 - Yongha Park, Chang-Hyo Yu, Kilwhan Lee, Hyunsuk Kim, Youngeun Park, Chun-Ho Kim, Yunseok Choi, Jinhong Oh, Changhoon Oh, Gurnrack Moon, Sangduk Kim, Horang Jang, Jin-Aeon Lee, Chinhyun Kim, Sungho Park:
72.5GFLOPS 240Mpixel/s 1080p 60fps multi-format video codec application processor enabled with GPGPU for fused multimedia application. 160-161 - Chao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications. 162-163 - Rahul Rithe, Priyanka Raina, Nathan Ickes, Srikanth V. Tenneti, Anantha P. Chandrakasan:
Reconfigurable processor for energy-scalable computational photography. 164-165 - Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS. 166-167 - Junyoung Park, Injoon Hong, Gyeonghoon Kim, Youchang Kim, Kyuho Jason Lee, Seongwook Park, Kyeongryeol Bong, Hoi-Jun Yoo:
A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition. 168-169 - Jafar Savoj, Chris Mangelsdorf:
Session 10 overview: Analog techniques. 170-171 - Milad Darvishi, Ronan A. R. van der Zee, Bram Nauta:
A 0.1-to-1.2GHz tunable 6th-order N-path channel-select filter with 0.6dB passband ripple and +7dBm blocker tolerance. 172-173 - Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski:
A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS. 174-175 - Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa:
A multi-path chopper-stabilized capacitively coupled operational amplifier with 20V-input-common-mode range and 3µV offset. 176-177 - Ippei Akita, Makoto Ishida:
A 0.06mm2 14nV/√Hz chopper instrumentation amplifier with automatic differential-pair matching. 178-179 - Marco Berkhout, Lutsen Dooper, Benno Krabbenborg, John Somberg:
A 4Ω 2.3W class-D audio amplifier with embedded DC-DC boost converter, current-sensing ADC and DSP for adaptive speaker protection. 180-181 - Jianlong Chen, Sasi Kumar Arunachalam, Todd Brooks, Iuri Mehr, Felix Cheung, Hariprasath Venkatram:
A 62mW stereo class-G headphone driver with 108dB dynamic range and 600µA/channel quiescent current. 182-183 - Arun Paidimarri, Danielle Griffith, Alice Wang, Anantha P. Chandrakasan, Gangadhar Burra:
A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability. 184-185 - Ying Cao, Paul Leroux, Wouter De Cock, Michiel Steyaert:
A 63, 000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback. 186-187 - Dong-Woo Jee, Dennis Sylvester, David T. Blaauw, Jae-Yoon Sim:
A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms. 188-189 - Fu-Lung Hsueh, Shinichiro Mutoh:
Session 11 overview: Emerging memory and wireless technology. 190-191 - Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan:
A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems. 192-193 - Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. 194-195 - David Ruffieux, Nicola Scolari, Frédéric Giroud, Thanh-Chau Le, Silvio Dalla Piazza, Felix Staub, Kai Zoschke, Charles Alix Manier, Hermann Oppermann, James Dekker, Tommi Suni, Giorgio Allegato:
A versatile timing microsystem based on wafer-level packaged XTAL/BAW resonators with sub-µW RTC mode and programmable HF clocks. 196-197 - Francesco Massel, Tero T. Heikkila, Juha-Matti Pirkkalainen, Sung-Un Cho, Heini Saloniemi, Pertti J. Hakonen, Mika A. Sillanpää:
Microwave amplification with nanomechanical resonators. 198-199 - Wataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. 200-201 - Hyunwoo Cho, Unsoo Ha, Taehwan Roh, Dongchurl Kim, Jeahyuck Lee, Yunje Oh, Hoi-Jun Yoo:
1.2Gb/s 3.9pJ/b mono-phase pulse-modulation inductive-coupling transceiver for mm-range board-to-board communication. 202-203 - Haruki Fukuda, Takahide Terada, Tadahiro Kuroda:
Retrodirective transponder array with universal on-sheet reference for wireless mobile sensor networks without battery or oscillator. 204-205 - Nachiket V. Desai, Jerald Yoo, Anantha P. Chandrakasan:
A scalable 2.9mW 1Mb/s eTextiles body area network transceiver with remotely powered sensors and bi-directional data communication. 206-207 - Jin-Man Han, Daniele Vimercati:
Session 12 overview: Non-volatile memory solutions. 208-209 - Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Sravanti Addepalli, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Saurabh Joshi, Achal Kathuria, Vincent Lai, Deep Masiwal, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Ronald Yin, Liping Peng, Jang Yong Kang, Sharon Huynh, Huijuan Wang, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Takahiko Hara, Hirofumi Inoue, Luca Fasoli, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader:
A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology. 210-211 - Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data. 212-213 - Noriyuki Miura, Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda:
A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×. 214-215 - Mihail Jefremow, Thomas Kern, Wolf Allers, Christian Peters, Jan Otterstedt, Othmane Bahlous, Karl Hofmann, Robert Allinger, Stephan Kassenetter, Doris Schmitt-Landsiedel:
Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS. 216-217 - Giovanni Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, Andrea D'Alessandro, Luca De Santis, Domenico Di Cicco, W. Di Francesco, M. L. Gallese, Girolamo Gallo, Michele Incarnati, C. Lattaro, Agostino Macerola, G. G. Marotta, Violante Moschiano, D. Orlandi, F. Paolini, S. Perugini, Luigi Pilolli, P. Pistilli, G. Rizzo, F. Rori, Massimo Rossini, Giovanni Santin, Emanuele Sirizotti, A. Smaniotto, U. Siciliani, Marco Tiburzi, R. Meyer, A. Goda, B. Filipiak, Tommaso Vali, Mark Helm, Ramin Ghodsi:
A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology. 218-219 - Akifumi Kawahara, Ken Kawai, Yuuichirou Ikeda, Yoshikazu Katoh, Ryotaro Azuma, Yuhei Yoshimoto, Kouhei Tanabe, Zhiqiang Wei, Takeki Ninomiya, Koji Katayama, Ryutaro Yasuhara, Shunsaku Muraoka, Atsushi Himeno, Naoki Yoshikawa, Hideaki Murase, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono:
Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAM. 220-221 - Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang:
A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. 222-223