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"Test Scheduling and Test Access Architecture Optimization for System-on-Chip."

Huan-Shan Hsu et al. (2002)

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DOI: 10.1109/ATS.2002.1181746

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  - https://dblp.org/rec/conf/ats/HsuHCWHWL02
Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411-

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