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ORCIDIEEE Transactions on Circuits and Systems II: Express Briefs, Volume 66
Volume 66-II, Number 1, January 2019
- Anders Jakobsson
, Adriana Serban, Shaofang Gong:
A Low-Noise RC-Based Phase Interpolator in 16-nm CMOS. 1-5 - Boon-Eu Seow, Shih-Tang Lin, Tzuen-Hsi Huang, Huey-Ru Chuang:
Injection Pulling Mitigation in CMOS Voltage-Controlled Oscillator Using A Novel Honeycomb-Shaped Planar Inductor. 6-10 - Sesha Sairam Regulagadda, Bibhudatta Sahoo, Ashudeb Dutta, K. Y. Varma, V. S. Rao:
A Packaged Noise-Canceling High-Gain Wideband Low Noise Amplifier. 11-15 - Dengquan Li, Zhangming Zhu, Ruixue Ding, Maliang Liu, Yintang Yang, Nan Sun:
A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration. 16-20 - Lei Guo, He Zhu, Amin M. Abbosh:
Phase Reconfigurable Microwave Power Divider. 21-25 - Yi Xie, Yuhua Liang, Maliang Liu, Shubin Liu, Zhangming Zhu:
A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm CMOS. 26-30 - Archit Joshi, Mukul Sarkar:
An Odd Phase CDR With Phase Interpolator Trimming. 31-35 - Yining Zhang, Haixin Song, Ranran Zhou, Woogeun Rhee, Inbo Shim, Zhihua Wang:
A Capacitor-Less Ripple-Less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range. 36-40 - Ali Rezapour, Hossein Shamsi:
Digital Noise Coupled MASH Delta-Sigma Modulator. 41-45 - Niksa Tadic, Alija Dervic, Milena Zogovic Erceg, Bernhard Goll, Horst Zimmermann:
A 54.2-dB Current Gain Dynamic Range, 1.78-GHz Gain-Bandwidth Product CMOS VCCA2. 46-50 - Eric Gutierrez, Carlos Perez, Luis Hernández, Fernando Cardes, Violeta Petrescu, Sergio Walter, Ulrich Gaier:
A Pulse Frequency Modulation VCO-ADC in 40 nm. 51-55 - Yuting Hou, Jiali Qu, Zhenzhen Tian, Mohamed Atef, Khalil Yousef, Yong Lian, Guoxing Wang:
A 61-nW Level-Crossing ADC With Adaptive Sampling for Biomedical Applications. 56-60 - Milan Salek, Xiaobang Shang, Robert C. Roberts, Michael J. Lancaster, Falko Boettcher, Daniel Weber, Thomas Starke:
W-Band Waveguide Bandpass Filters Fabricated by Micro Laser Sintering. 61-65 - Yilong Liao, Xiangning Fan, Zaijun Hua:
Influence of LFSR Dither on the Periods of a MASH Digital Delta-Sigma Modulator. 66-70 - Haohong Yu, Yong Chen, Chirn Chye Boon, Chenyang Li, Pui-In Mak, Rui Paulo Martins:
A 0.044-mm2 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB. 71-75 - Wei Lu, Yu Liang, Yanyan Liu, Zhibin Liang, Wei Zhang:
The Design of an RS Decoder Based on the mCS-RiBM Algorithm for 100 Gb/s Optical Communication Systems. 76-80 - Jack Ou, Pietro M. Ferreira:
Implications of Small Geometry Effects on gm/ID Based Design Methodology for Analog Circuits. 81-85 - Guoqi Ma, Masood Ghasemi, Xingyong Song:
Event-Triggered Modified Repetitive Control for Periodic Signal Tracking. 86-90 - Ateeq Ur Rehman, Muhammad Rehan, Naeem Iqbal, Choon Ki Ahn:
Toward the LPV Approach for Adaptive Distributed Consensus of Lipschitz Multi-Agents. 91-95 - Weiguo Lu, Yixiao Ruan, Zhaoyang Zhao, Herbert H. C. Iu:
Auxiliary Parallel Inductor Switching Control for Improving the Load Transient Response Performance of Buck Converters. 96-100 - Junichi Kashiwagi, Atsushi Yamaguchi, Yohei Moriyama, Ken Nakahara:
Hysteretic Control Embedded Boost Converter Operating at 25-MHz Switching. 101-105 - Yinghui Tian, Yong Hei, Zhizhe Liu, Qi Shen, Zhixiong Di, Tao Chen:
A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design. 106-110 - Huan Zhang, Bei Zhao, Wei-Jun Li, Zhen-Guo Ma, Feng Yu:
Resource-Efficient Parallel Tree-Based Join Architecture on FPGA. 111-115 - Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang:
A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. 116-120 - Xiang Feng, Shuguo Li:
Accelerating an FHE Integer Multiplier Using Negative Wrapped Convolution and Ping-Pong FFT. 121-125 - Haicheng Tu, Yongxiang Xia, Herbert Ho-Ching Iu, Xi Chen:
Optimal Robustness in Power Grids From a Network Science Perspective. 126-130 - Peican Zhu, Qiang Zhi, Zhen Wang, Yangming Guo:
Stochastic Analysis and Optimal Design of Majority Systems. 131-135 - Moslem Nouri, Mohsen Hayati, Teresa Serrano-Gotarredona, Derek Abbott:
A Digital Neuromorphic Realization of the 2-D Wilson Neuron Model. 136-140 - Weifeng Xia, Wei Xing Zheng, Shengyuan Xu:
Realizability Condition for Digital Filters With Time Delay Using Generalized Overflow Arithmetic. 141-145 - Mahdi Kalbasi, Hooman Nikmehr:
A Fine-Grained Pipelined 2-D Convolver for High-Performance Applications. 146-150 - Hamidreza Sadreazami, Marzieh Amini:
A Robust Image Watermarking Scheme Using Local Statistical Distribution in the Contourlet Domain. 151-155
Volume 66, Number 2, February 2019
- Tongquan Jiang, Jun Yin, Pui-In Mak, Rui Paulo Martins:
A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM. 157-161 - Abhishek Bhat, Nagendra Krishnapura:
On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration. 162-166 - Debashis Mandal, Chirag Desai, Bertan Bakkaloglu, Sayfe Kiaei:
Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time. 167-171 - Amir Fathi, Abdollah Khoei, Morteza Mousazadeh:
Generalized Method of Analog Circuit Characteristic Function Analysis. 172-176 - Che-Wei Tien, Shen-Iuan Liu:
A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector. 177-181 - Jiye Lim, Jintae Kim:
A 20-kHz~16-MHz Programmable-Bandwidth 4th Order Active Filter Using Gain-Boosted Opamp With Negative Resistance in 65-nm CMOS. 182-186 - Devon Janke, Andrew Monk, Eric Swindlehurst, Kent D. Layton, Shiuh-Hua Wood Chiang:
A 9-Bit 10-MHz 28-µW SAR ADC Using Tapered Bit Periods and a Partially Interdigitated DAC. 187-191 - Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim:
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth. 192-196 - Fanyang Li, Shuying Cheng:
A Highly Digital ADC With Enhanced Accuracy Using a Simple Ripple-Transferring Replica Pseudo PLL Technique. 197-201 - Xin Ding, Jianhui Wu, Chao Chen:
A Low-Power 0.6-V Quadrature VCO With a Coupling Current Reuse Technique. 202-206 - Rim Barrak, Ali Othman, Ghalid Idir Abib, Muriel Muller, Mohamed Mabrouk, Adel Ghazel:
Design of a Tunable Anti-Aliasing Filter for Multistandard RF Subsampling GNSS Receivers. 207-211 - Bowen Ding, Shengyue Yuan, Chen Zhao, Li Tao, Tong Tian:
A Ka Band FMCW Transceiver Front-End With 2-GHz Bandwidth in 65-nm CMOS. 212-216 - Hyobeen Park, Myoungseok Yu, Yunho Jung, Seongjoo Lee:
Design of Reconfigurable Digital IF Filter With Low Complexity. 217-221 - Yong-Chang Choi, Mauricio Velazquez Lopez, Sounghun Shin, Sang-Sun Yoo, Hyung-Joun Yoo:
A Fully Digital Phase Modulator With a Highly Linear Phase Calibration Loop for Wideband Polar Transmitters. 222-226 - Yangcan Zhou, Zhiyu Chen, Jun Lin, Zhongfeng Wang:
A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing. 227-231 - Dongin Kim, SeongHwan Cho:
A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise. 232-236 - Chee-Cheow Lim, Harikrishnan Ramiah, Jun Yin, Narendra Kumar, Pui-In Mak, Rui Paulo Martins:
A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM. 237-241 - Nasim Nasirian, Reza Soosahabi, Magdy A. Bayoumi:
Probabilistic Analysis of Power-Gating in Network-on-Chip Routers. 242-246 - Xiangyi Wei, Wenwu Yu, He Wang, Yiyang Yao, Feng Mei:
An Observer-Based Fixed-Time Consensus Control for Second-Order Multi-Agent Systems With Disturbances. 247-251 - Mengmou Li:
Generalized Lagrange Multiplier Method and KKT Conditions With an Application to Distributed Optimization. 252-256 - Tsung-Wei Hsu, Hung-Hsien Wu, Dian-Lin Tsai, Chia-Ling Wei:
Photovoltaic Energy Harvester With Fractional Open-Circuit Voltage Based Maximum Power Point Tracking Circuit. 257-261 - Agasthya Ayachit, Marian K. Kazimierczuk:
Averaged Small-Signal Model of PWM DC-DC Converters in CCM Including Switching Power Loss. 262-266 - Yongkang Xiong, Yongqiang Ye:
Physical Interpretations of Grid Voltage Full Feedforward for Grid-Tied Inverter. 267-271 - Seungsik Moon, Sungsoo Park, Jae-Ho Lee, Youngjoo Lee:
Rapid Balise Telegram Decoder With Modified LFSR Architecture for Train Protection Systems. 272-276 - Jinshan Yue, Yongpan Liu, Zhe Yuan, Zhibo Wang, Qingwei Guo, Jinyang Li, Chengmo Yang, Huazhong Yang:
A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization. 277-281 - Siew-Kei Lam, Guiyuan Jiang, Meiqing Wu, Bin Cao:
Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector. 282-286 - Aibin Yan, Kang Yang, Zhengfeng Huang, Jiliang Zhang, Jie Cui, Xiangsheng Fang, Maoxiang Yi, Xiaoqing Wen:
A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application. 287-291 - Basant Kumar Mohanty:
Efficient Fixed-Width Adder-Tree Design. 292-296 - Robin Kalyan, Karun Rawat, Shiban K. Koul:
A Digitally Assisted Dual-Input Dual-Band Doherty Power Amplifier With Enhanced Efficiency and Linearity. 297-301 - Noussaiba Gasmi, Mohamed Boutayeb, Assem Thabet, Mohamed Aoun:
Sliding Window Based Nonlinear H∞ Filtering: Design and Experimental Results. 302-306 - Yicong He, Fei Wang, Shiyuan Wang, Pengju Ren, Badong Chen:
Maximum Total Correntropy Diffusion Adaptation Over Networks With Noisy Links. 307-311 - Xuerong Li, Hongli Dong, Zidong Wang, Fei Han:
Set-Membership Filtering for State-Saturated Systems With Mixed Time-Delays Under Weighted Try-Once-Discard Protocol. 312-316
Volume 66, Number 3, March 2019
- Xiao-Kun Bi, Teng Cheng, Pedro Cheong, Sut-Kam Ho, Kam-Weng Tam:
Design of Dual-Band Bandpass Filters With Fixed and Reconfigurable Bandwidths Based on Terminated Cross-Shaped Resonators. 317-321 - Xiao Wang, Fule Li, Wen Jia, Zhihua Wang:
A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration. 322-326 - Boyu Shen, Soumya Bose, Matthew L. Johnston:
A 1.2 V-20 V Closed-Loop Charge Pump for High Dynamic Range Photodetector Array Biasing. 327-331 - Congyi Zhu, Jun Lin, Zhongfeng Wang:
A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs. 332-336 - Kyoungwoon Kim, Cam Nguyen:
A V-Band Power Amplifier With Integrated Wilkinson Power Dividers-Combiners and Transformers in 0.18- $\mu$ m SiGe BiCMOS. 337-341 - Alfian Abdi, Hyung Seok Kim, Hyouk-Kyu Cha:
A High-Voltage Generation Charge-Pump IC Using Input Voltage Modulated Regulation for Neural Implant Devices. 342-346 - Hossein Mirzaie, Hamidreza Maghami, Ramin Zanbaghi, Pedram Payandehnia, Kartikeya Mayaram, Terri S. Fiez:
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA. 347-351 - Hasan Molaei, Khosrow Hajsadeghi:
A 5.3-ps, 8-b Time to Digital Converter Using a New Gain-Reconfigurable Time Amplifier. 352-356 - Congyi Zhu, Jun Lin, Zhongfeng Wang:
Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs. 357-361 - Dae Hyun Kwon, Minkyu Kim, Sung-Geun Kim, Woo-Young Choi:
A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector. 362-366 - Yang Zhang, Xiao-Yong He, Kong-Pang Pun:
An Extremely Linear Multi-Level DAC for Continuous-Time Delta-Sigma Modulators. 367-371 - Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim:
A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner. 372-376 - Kyoohyun Noh, Minglei Zhang, Edgar Sánchez-Sinencio:
A Unified Amplifier-Based CC-CV Linear Charger for Energy-Constrained Low-Power Applications. 377-381 - Sri Harsh Pakala, Punith R. Surkanti, Paul M. Furth:
A Spread-Spectrum Mode Enabled Ripple-Based Buck Converter Using a Clockless Frequency Control. 382-386 - Bahar Youssefi, Alexander J. Leigh, Mitra Mirhassani, Q. M. Jonathan Wu:
Tunable Neuron With PWL Approximation Based on the Minimum Operator. 387-391 - Sunder S. Kidambi:
On the Design of Optimal Noise Transfer Functions for Delta-Sigma Modulators. 392-396 - Hangxuan Cui, Jun Lin, Zhongfeng Wang:
An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes. 397-401 - Farzad Etemadi, Payam Heydari, Hamid Jafarkhani:
On Analog QAM Demodulation for Millimeter-Wave Communications. 402-406 - Siqi Wang, Morgan Roger, Caroline Lelandais-Perrault:
Impacts of Crest Factor Reduction and Digital Predistortion on Linearity and Power Efficiency of Power Amplifiers. 407-411 - Xinmiao Zhang:
A Low-Power Parallel Architecture for Linear Feedback Shift Registers. 412-416 - Lei Qiu, Supeng Liu, Zhongyuan Fang, Yuanjin Zheng:
An Adaptive Beamforming Technique for UWB Impulse Transceiver. 417-421 - Yao-Lin Jiang, Zhen-Zhong Qi, Ping Yang:
Model Order Reduction of Linear Systems via the Cross Gramian and SVD. 422-426 - Kasi V. Ramana, Somanath Majhi, Anup Kumar Gogoi:
Modeling and Estimation of DC-DC Buck Converter Dynamics Using Relay Feedback Output With Performance Evaluation. 427-431 - Yaqi Wang, Jianquan Lu, Jinling Liang, Jinde Cao, Matjaz Perc:
Pinning Synchronization of Nonlinear Coupled Lur'e Networks Under Hybrid Impulses. 432-436 - Jin Zhou, Xinghuo Yu, Junan Lu:
Node Importance in Controlled Complex Networks. 437-441 - (Withdrawn) An Adaptive Event-Triggered Synchronization Approach for Chaotic Lur'e Systems Subject to Aperiodic Sampled Data. 442-446
- Weinan Gao, Yu Jiang, Masoud Davari:
Data-Driven Cooperative Output Regulation of Multi-Agent Systems via Robust Adaptive Dynamic Programming. 447-451 - Chunyu Yang, Zhiyuan Che, Jun Fu, Linna Zhou:
Passivity-Based Integral Sliding Mode Control and $\varepsilon$ - Bound Estimation for Uncertain Singularly Perturbed Systems With Disturbances. 452-456 - Tao Peng, Hongwei Tao, Chao Yang, Zhiwen Chen, Chunhua Yang, Weihua Gui, Hamid Reza Karimi:
A Uniform Modeling Method Based on Open-Circuit Faults Analysis for NPC-Three-Level Converter. 457-461 - Jun Tang, Jaeseong Lee, Jeongjin Roh:
Low-Power Fast-Transient Capacitor-Less LDO Regulator With High Slew-Rate Class-AB Amplifier. 462-466 - Jung-Duk Suh, Jinmin Seok, Bai-Sun Kong:
A Fast Response PWM Buck Converter With Active Ramp Tracking Control in a Load Transient Period. 467-471 - Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA. 472-476 - Yinqi Tang, Jintao Zhang, Naveen Verma:
Scaling Up In-Memory-Computing Classifiers via Boosted Feature Subsets in Banked Architectures. 477-481 - Haolin Li, Laurens Breyne, Joris Van Kerrebrouck, Michiel Verplaetse, Chia-Yi Wu, Piet Demeester, Guy Torfs:
A 21-GS/s Single-Bit Second-Order Delta-Sigma Modulator for FPGAs. 482-486 - Xiaoling Xiong, Xinbo Ruan:
Non-Smooth Bifurcation Analysis of Multi-Structure Multi-Operating-Mode Power Electronics Systems for Applications With Renewable Energy Sources. 487-491 - Rushi Lan, Jinwen He, Shouhua Wang, Yining Liu, Xiaonan Luo:
A Parameter-Selection-Based Chaotic System. 492-496 - Ravi Tharaka Wijesekara, Chamira U. S. Edussooriya, Len T. Bruton, Panajotis Agathoklis:
A 3-D Sparse FIR Frustum Filter for Enhancing Broadband Plane Waves. 497-501 - Rongqiang Zhao, Qiang Wang:
Learning Separable Dictionaries for Sparse Tensor Representation: An Online Approach. 502-506 - Mohammad Shams Esfand Abadi, Mohammad Javad Ahmadi:
Diffusion Improved Multiband-Structured Subband Adaptive Filter Algorithm With Dynamic Selection of Nodes Over Distributed Networks. 507-511 - Omid Saatlou, M. Omair Ahmad, M. N. S. Swamy:
Joint Data and Pilot Power Allocation for Massive MU-MIMO Downlink TDD Systems. 512-516
Volume 66-II, Number 4, April 2019
- Shuenn-Yuh Lee, Chun-Jung Chiu, Hao-Yun Lee:
Systematic Analysis of Quadrature VCO With Capacitive Source Degeneration Coupling and Spontaneous Transconductance Matching Techniques. 517-521 - Jia Sun, Timo Rahkonen:
Speed-Up Technique by Pre-Charging Load Capacitor in a SC Residue Circuit. 522-526 - Iat-Fai Sun, Jun Yin, Pui-In Mak, Rui Paulo Martins:
A Comparative Study of 8-Phase Feedforward-Coupling Ring VCOs. 527-531 - Yoshihiro Tohma:
The Transfer Function of Amplitude Modulation Circuits Using Varactor Diode. 532-536 - Ali Reza Dehqan, Siroos Toofan, Hadi Lotfi:
Floating Bulk Cascode Class-E Power Amplifier. 537-541 - Jabeom Koo, Keping Wang, Richard C. Ruby, Brian P. Otis:
A 2-GHz FBAR-Based Transformer Coupled Oscillator Design With Phase Noise Reduction. 542-546 - Leila Safari, Gianluca Barile, Vincenzo Stornelli, Giuseppe Ferri:
An Overview on the Second Generation Voltage Conveyor: Features, Design and Applications. 547-551 - Huajun Zhang, Zhichao Tan, Yi Zhang, Baozhen Chen, Roberto Maurino, Robert Adams, Khiem Nguyen:
A 6 $\mu$ W 95 dB SNDR Inverter Based $\Sigma\Delta$ Modulator With Subtractive Dithering and SAR Quantizer. 552-556 - Darya Mohtashemi, Michael M. Green:
A Low-Power 8-GS/s Comparator for High-Speed Analog-to-Digital Conversion in $0.13\mu$ m CMOS Technology. 557-561