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ORCID9th ASICON 2011: Xiamen, China
- 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011. IEEE 2011, ISBN 978-1-61284-192-2
- Ting-Ao Tang:
Welcome to ASICON 2011. VII - Jiongyao Ye, Jiannan Jin, Takahiro Watanabe:
A behavior-based reconfigurable cache for the low-power embedded processor. 1-5 - Ting Zhang, Lan Chen, Yan Feng:
A novel method for storage architecture of pipeline FFT processor. 6-8 - Yuejun Zhang
, Pengjun Wang, Lipeng Hao:
Design of resistant DPA three-valued counter based on SABL. 9-12 - Qiankun Yang, Pengjun Wang, Fengna Mei:
Improvement of adiabatic domino circuits and its application in multi-valued circuits. 13-16 - Jinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh:
Low power shift registers for megabits CMOS image sensors. 17-20 - Ying Cui, Xiao Peng, Yu Jin, Peilin Liu, Shinji Kimura, Satoshi Goto:
High-parallel LDPC decoder with power gating design. 21-24 - Wenqi Bao, Jiang Jiang, Qing Sun, Yuzhuo Fu:
A reconfigurable macro-pipelined DCT/IDCT accelerator. 25-28 - Ling Li, Teng Wang, Ziyi Hu, Xin'an Wang, Xu Zhang:
Scheduling to timing optimization for a novel high-level synthesis approach. 29-32 - Yimiao Zhao, Zhigang Ni:
High reliable digital signal processor for automotive application. 33-34 - Pengjun Wang, Lipeng Hao:
A novel Differential fault analysis on AES-128. 35-38 - Minh Thien Trieu, Huong Thien Hoang, Phong The Vo, Hung Bao Vo, Yoichi Yuyama:
Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU. 39-42 - Sha Shen, Huibo Zhong, Yibo Fan, Xiaoyang Zeng:
A hardware/software co-design approach for multiple-standard video bitstream parsing. 43-46 - Jinn-Shyan Wang, Yung-Chen Chien, Jia-Hong Lin, Chun-Yuan Cheng, Ying-Ting Ma, Chung-Hsun Huang:
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. 47-50 - Junbao Liu, Shuai Wang, Yang Li, Jun Han, Xiaoyang Zeng:
Analysis of adaptive support-weight based stereo matching for hardware realization. 51-54 - Qing Sun, Yuzhuo Fu, Wenqi Bao, Jiang Jiang:
A high performance sound source localization system based on macro-pipelined architecture. 55-58 - Wei Li, Xuan Yang, Zibin Dai:
Research on design of a reconfigurable parallel structure targeted at LFSR. 59-63 - Zhongyi Han, Jianing Wang, Yizhong Zeng, Zhongwen Hu:
Using NOC technology to improve photoelectric encoder system for LAMOST spectroscopes. 64-66 - Zhidong Mao, Liguang Chen, Yuan Wang, Jinmei Lai:
A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain. 67-70 - Tuan Minh Phan Ho, Thang Minh Le, Khanh Duy Vu, Seiji Mochizuki, Kenichi Iwata, Keisuke Matsumoto, Hiroshi Ueda:
A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder. 71-74 - Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A two-way parallel CAVLC encoder for 4K×2K H.264/AVC. 75-78 - Yu Jin, Shinji Kimura:
Multi-stage power gating based on controlling values of logic gates. 79-82 - Weina Zhou, Yao Zou, Lin Dai, Xiaoyang Zeng:
A high speed reconfigurable face detection architecture. 83-86 - Kanwen Wang, Shuai Chen, Wei Cao, Lingli Wang, Jiarong Tong:
A coarse-grained reconfigurable computing unit. 87-90 - Sahana Swarup, Sheldon X.-D. Tan, Zao Liu, Hai Wang, Zhigang Hao, Guoyong Shi:
Battery state of charge estimation using adaptive subspace identification method. 91-94 - Jiake Wang, Jinguang Jiang, Shanshan Li, Xu Gong, Xifeng Zhou, Qingyun Li:
A new frequency compensation scheme for current-mode DC/DC converter. 95-99 - Ze-kun Zhou, Huifang Wang, Yue Shi, Xin Ming, Bo Zhang:
A high-performance PWM controller with adjustable current limit. 100-103 - Xiao Tang, Lenian He:
Capacitor-free, fast transient response CMOS low-dropout regulator with multiple-loop control. 104-107 - Yanzhao Ma, Jun Cheng, Guican Chen:
A high efficiency current mode step-up/step-down DC-DC converter with smooth transition. 108-111 - Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara:
A non-rectifier wireless power transmission system using on-chip inductor. 112-115 - Oi-Ying Wong, Hei Wong, Wing-Shan Tam, Chi-Wah Kok:
An overview of charge pumping circuits for flash memory applications. 116-119 - Peng Zhang, Fan Ye, Junyan Ren:
Class-AB CMOS buffer with floating class-AB control. 120-123 - Guoyuan Fu, H. Alan Mantooth, Jia Di:
A new topology for fully differential amplifiers that enhances their tolerance to external disturbances. 124-127 - Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara:
Double charge pump circuit with triple charge sharing clock scheme. 128-132 - Seung-Jae Choi, Young-Hyun Jun, Bai-Sun Kong:
CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction. 133-136 - Doo Hyung Woo, Ilku Nam, Joonwoo Choi:
ROIC with adaptive reset control for improving dynamic range of IR FPAs. 137-140 - Wengang Huang, Chenghe Wang, Luncai Liu, Xiaozong Huang, Guoqiang Wang:
A signal conditioner IC for inductive proximity sensors. 141-144 - Jinghao Feng, Na Yan, Hao Min:
A low-power low-noise amplifier for EEG/ECG signal recording applications. 145-148 - Tao Yin, Huanming Wu, Qisong Wu, Haigang Yang, Jiwei Jiao:
A TIA-based interface for MEMS capacitive gyroscope. 149-152 - Jian Wang, Andreas Karlsson, Joar Sohl, Magnus Pettersson, Dake Liu:
A multi-level arbitration and topology free streaming network for chip multiprocessor. 153-158 - Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song:
Design and verification of an application-specific PLD using VHDL and SystemVerilog. 159-162 - Chaochao Feng, Jinwen Li, Zhonghai Lu, Axel Jantsch, Minxuan Zhang:
Evaluation of deflection routing on various NoC topologies. 163-166 - Hongming Chen, Xiaoyuan Chen, Tie Liu, Yuhua Cheng:
ASIC implementation of an OFDM baseband transceiver for HINOC. 167-170 - Yangfan Zhou, Zhongxiang Cao, Quanliang Li, Qi Qin, Nanjian Wu:
Design of four-transistor Pixel for high speed CMOS image. 171-174 - Yuan Wen Hau, Muhammad N. Marsono, Chia Yee Ooi, Mohamed Khalil Hani:
A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip. 175-179 - Shih-Chang Chang, I-Jen Chao, Bin-Da Liu, Chun-Yueh Huang, Mei-Hwa Lee, Hung-Yin Lin:
Design of a signal processing circuit for quartz crystal microbalance biosensors. 180-183 - Jinyu Zhu, Liji Wu, Xiangmin Zhang, Chen Jia, Chun Zhang:
A low-power 433MHz transmitter for battery-less Tire Pressure Monitoring System. 184-187 - Longjun Liu, Hongbin Sun, Wenzhe Zhao, Zuoxun Hou, Jingmin Xin, Nanning Zheng:
A high performance and low cost video processing SoC for digital HDTV systems. 188-191 - Jin Huang, Jing Xie, Zhigang Mao:
A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications. 192-195 - Yang Li, Jun Han, Shuai Wang, Junbao Liu, Xiaoyang Zeng:
A NoC-based multi-core architecture for IEEE 802.11i CCMP. 196-199 - Jiayi Sheng, Liulin Zhong, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
A method of quadratic programming for mapping on NoC architecture. 200-203 - Maofei He, Jiajie Zhang, Wenhua Fan, Zhiyi Yu, Xiaoyang Zeng:
A channel estimator for LTE downlink mapped on a multi-core processor platform. 204-207 - Lian Huai, Gerald E. Sobelman, Xiaofang Zhou:
Wideband spectrum sensing using the all-phase FFT. 208-211 - Chen Chen, Yuebin Huang, Yizhi Wang, Yun Chen, Xiaoyang Zeng:
A robust frame synchronization scheme for Broadband Power-line Communication. 212-215 - Zhang Zhang, Dongge Wang, Yuteng Pan, Dan Wang, Xiaofang Zhou, Gerald E. Sobelman:
FFT implementation with Multi-operand floating point units. 216-219 - Yan Zhao, Jinyuan Zhou, Xiaofang Zhou, Gerald E. Sobelman:
General lattice wave digital filter with phase compensation scheme. 220-223 - Shouyi Yin, Jianwei Cui, Ao Luo, Leibo Liu, Shaojun Wei:
A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems. 224-227 - Jikang Xia, Lan Chen, Ying Li, Yinhao Zhou:
System modeling and analysis of the IEEE 802.15.4 physical layer design. 228-231 - Xiaoqing Wen:
Towards the next generation of low-power test technologies. 232-235 - Chong Zhang, Tsutomu Yoshihara:
Word error control algorithm through multi-reading for NAND Flash memories. 236-239 - Lei Wang, Jianhua Jiang, Yumei Zhou, Gaofeng Ren:
A new scheme for testability improvement of ECC incorporated memory. 240-243 - Bing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin:
A BIST scheme for high-speed Gain Cell eDRAM. 244-247 - Chingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang:
Variation-resilient voltage generation for SRAM weak cell testing. 248-251 - Ramin Rajaei, Mahmoud Tabandeh, Bizhan Rashidian:
Single event upset immune latch circuit design using C-element. 252-255 - Juin J. Liou, Chang Jiang, Cao Guang-Biao, Chang Gung, Feng Chia:
Challenges of electrostatic discharge (ESD) protection in emerging silicon nanowire technology. 256-258 - Kuen-Jong Lee, Alan P. Su, Long-Feng Chen, Jia-Wei Jhou, Jiff Kuo, Mark Liu:
A software/hardware co-debug platform for multi-core systems. 259-262 - Gu Cong, Chen Hong:
HV CMOS orientated variation-aware layout and robust solution. 263-266 - Yueming Yang, Heng Quan, Zewen Shi, Xiaoyang Zeng, Zhiyi Yu:
Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs. 267-270 - Arash Abtahi Forooshani, Fakhrul Zaman Rokhani:
Addressing fault tolerance in 4-PAM signaling by using block codes for on/off-chip communication. 271-274 - Peng Zhang, Yuan Wang, Song Jia, Xing Zhang:
A novel multi-finger layout strategy for GGnMOS ESD protection device. 275-278 - Byeungchul Kim, Yoon-Jong Song, Sujin Ahn, Younseon Kang, Hoon Jeong, Dongho Ahn, Seokwoo Nam, Gitae Jeong, Chilhee Chung:
Current status and future prospect of Phase Change Memory. 279-282 - Kwan-Hee Jo, Chul-Moon Jung, Kyeong-Sik Min:
Memristor models and circuits for controlling Process-VDD-Temperature variations. 283-286 - Hao Yan, Donghui Wang, Chaohuan Hou:
The design of low leakage SRAM cell with high SNM. 287-290 - Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin:
Novel RRAM programming technology for instant-on and high-security FPGAs. 291-294 - Wenbin Liu, Jinhui Wang, Wuchen Wu, Xiaohong Peng, Ligang Hou:
A study of dual-Vt configurations of an 8T SRAM cell in 45nm. 295-298 - Meng-Fan Chang, Pi-Feng Chiu, Wei-Cheng Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu:
Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM). 299-302 - Zhao-Yong Zhang, Li-Jun Zhang, Yi-Ping Zhang, Rui Feng Huang, Shou-Dao Wu, Jian-Bin Zheng:
A 55nm ultra high density two-port register file compiler with improved write replica technique. 303-306 - Ruifeng Huang, Jianbin Zheng, Lijun Zhang, Zhaoyong Zhang, Hao Wu, Yue Yu:
Word line boost and read SA PMOS compensation (SAPC) for ROM in 55nm CMOS. 307-310 - Baoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Design of a single-ended cell based 65nm 32×32b 4R2W register file. 311-314 - Hongwei Hong, Zheng Li, Qin Li, Ruizhe Wang, Charlie Hwang:
A 90 nm 16 Mb embedded phase-change memory macro with write current smoothing and enhanced write bandwidth. 315-318 - Goro Suzuki:
Separate projection and extended Cauer method for circuit reduction. 319-323 - Nobuyuki Mihara, Goro Suzuki:
VLSI interconnect delay analysis method for ramp input signal. 324-328 - Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno:
RRA-based multi-objective optimization to mitigate the worst cases of placement. 329-332 - Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye:
Numerical characterization of multi-dielectric green's function for floating random walk based capacitance extraction. 333-336 - Peng Du, Shih-Hung Weng, Xiang Hu, Chung-Kuan Cheng:
Power grid sizing via convex programming. 337-340 - Huihong Zhang, Pengjun Wang:
Polarity optimization of XNOR/OR circuit area and power based on weighted sum method. 341-344 - Lisa Piper, Jin Zhang:
Don't let the X-bugs bite: Conquer elusive X-propagation issues early! Get them before they get you! 345-348 - Menwang Xie, Duoli Zhang, Yao Li:
Meshim: A high-level performance simulation platform for three-dimensional network-on-chip. 349-352 - Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto:
Through-Silicon-Via assignment for 3D ICs. 353-356 - Jia Liu, Yuchun Ma, Ning Xu, Yu Wang:
Incremental layout optimization for NoC designs based on MILP formulation. 357-360 - Jianping Hu, Jun Wang:
Standard cell design of a low-leakage flip-flop with gate-length biasing. 361-364 - Akitoshi Matsuda, Jin Zhang:
Debugging methodology and timing analysis in CDC solution. 365-368 - Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng:
Circuit simulation using matrix exponential method. 369-372 - Haocheng Huang, Aiwu Ruan, Yongbo Liao, Jianhua Zhu, Lin Wang, Chuanyin Xiang, Pin Li:
A new event driven testbench synthesis engine for FPGA emulation. 373-376 - Xianyang Jiang, Ying Liu, Shilei Sun, Gaofeng Wang:
An improved packing tool based on a dual-output basic logic element. 377-380 - Quanquan Li, Yingke Gao, Tiejun Zhang, Chaohuan Hou:
A test approach of combining partial scan with functional testing for high performance processors. 381-384 - Chaofan Yu, Lingli Wang, Xuegong Zhou:
Automatic layout generator for embedded FPGA cores. 385-388 - Liulin Zhong, Jiayi Sheng, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Dian Zhou:
An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture. 389-392 - Xiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai:
FPGA interconnect timing library based on the statistical method. 393-396 - Suoming Pu, Bo Yu, Xuan Zou:
Robustness and performance analysis on high speed ASIC design with canonical statistical timing model. 397-400 - Meng Yang, Hongying Xu:
Optimization of mixed polarity Reed-Muller expressions based on Whole Annealing Genetic Algorithm. 401-404 - Mark P. C. Mok, Kenneth C. K. Lo, Yuzhong Jiao, Yiu Kei Li:
CPIPQ: A common platform for silicon IP qualification. 405-408 - Huang Kun, Guoxing Zhao, Yang Xu, Zuying Luo:
Comprehensive electro-thermal(ET) analysis with considering ET coupling. 409-412 - Jiawen Wang, Li Li, Hongbing Pan, Shuzhuan He, Rong Zhang:
Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm. 413-416 - Song Chen, Yuan Yao, Takeshi Yoshimura:
Mobility overlap-removal based timing-constrained scheduling. 417-420 - Xiaolin Zhang, Zhi Lin, Song Chen, Takeshi Yoshimura:
An effecient level-shifter floorplanning method for Multi-voltage design. 421-424 - Tingkai Li:
The manufacturing of Si base thin film solar cell modules. 425-429 - Xiaomeng Chen:
Challenges and strategies in advanced CMOS technology development. 430-432 - Keqiang Qian, Wen Luo, Qi Yu:
Research on electromechanical model of micro-accelerometer based on SOI technology. 433-436 - Xiaoxu Kang, Qingyun Zuo, Jiaqing Li, Chao Yuan, Yuhang Zhao:
CMOS compatible MEMs process for post interconnect single chip integration application. 437-440 - Xifeng Zhou, Jinguang Jiang, Shanshan Li:
Cascadable current-mode multifunction filter configuration using minimum number of CCTAs and grounded capacitors. 441-444 - Xiaoyu Wang, Haigang Yang, Tao Yin, Fei Liu:
A matrix approach to low-voltage low-power log-domain CMOS current-mode adjustable-bandwidth step-gain filter design. 445-448 - Luo Wang, Huihui Ji, Quan Sun:
A sigma-delta modulator with a novel chopper correlated double sampled integrator. 449-452 - Jing Li, Ran Li, Ting Yi, Zhiliang Hong, Bill Yang Liu:
VLSI implementation of high-speed low power decimation filter for LTE sigma-delta A/D converter application. 453-456 - Siliang Hua, Hao Yan, Yan Liu, Donghui Wang, Chaohuan Hou:
A continuous time sigma-delta modulator using time-domain quantizer and feedback element. 457-460 - Daehwa Paik, Masaya Miyahara, Akira Matsuzawa:
An analysis on a pseudo-differential dynamic comparator with load capacitance calibration. 461-464 - Hong Chang, Wenxian Lu, Xu Cheng, Yawei Guo, Xiaoyang Zeng:
Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications. 465-468 - Young-Hwa Kim, SeongHwan Cho:
A time-domain flash ADC immune to voltage controlled delay line non-linearity. 469-471