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ORCID9th ASICON 2011: Xiamen, China
- 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011. IEEE 2011, ISBN 978-1-61284-192-2
- Ting-Ao Tang:
Welcome to ASICON 2011. VII - Jiongyao Ye, Jiannan Jin, Takahiro Watanabe:
A behavior-based reconfigurable cache for the low-power embedded processor. 1-5 - Ting Zhang, Lan Chen, Yan Feng:
A novel method for storage architecture of pipeline FFT processor. 6-8 - Yuejun Zhang
, Pengjun Wang, Lipeng Hao:
Design of resistant DPA three-valued counter based on SABL. 9-12 - Qiankun Yang, Pengjun Wang, Fengna Mei:
Improvement of adiabatic domino circuits and its application in multi-valued circuits. 13-16 - Jinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh:
Low power shift registers for megabits CMOS image sensors. 17-20 - Ying Cui, Xiao Peng, Yu Jin, Peilin Liu, Shinji Kimura, Satoshi Goto:
High-parallel LDPC decoder with power gating design. 21-24 - Wenqi Bao, Jiang Jiang, Qing Sun, Yuzhuo Fu:
A reconfigurable macro-pipelined DCT/IDCT accelerator. 25-28 - Ling Li, Teng Wang, Ziyi Hu, Xin'an Wang, Xu Zhang:
Scheduling to timing optimization for a novel high-level synthesis approach. 29-32 - Yimiao Zhao, Zhigang Ni:
High reliable digital signal processor for automotive application. 33-34 - Pengjun Wang, Lipeng Hao:
A novel Differential fault analysis on AES-128. 35-38 - Minh Thien Trieu, Huong Thien Hoang, Phong The Vo, Hung Bao Vo, Yoichi Yuyama:
Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU. 39-42 - Sha Shen, Huibo Zhong, Yibo Fan, Xiaoyang Zeng:
A hardware/software co-design approach for multiple-standard video bitstream parsing. 43-46 - Jinn-Shyan Wang, Yung-Chen Chien, Jia-Hong Lin, Chun-Yuan Cheng, Ying-Ting Ma, Chung-Hsun Huang:
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. 47-50 - Junbao Liu, Shuai Wang, Yang Li, Jun Han, Xiaoyang Zeng:
Analysis of adaptive support-weight based stereo matching for hardware realization. 51-54 - Qing Sun, Yuzhuo Fu, Wenqi Bao, Jiang Jiang:
A high performance sound source localization system based on macro-pipelined architecture. 55-58 - Wei Li, Xuan Yang, Zibin Dai:
Research on design of a reconfigurable parallel structure targeted at LFSR. 59-63 - Zhongyi Han, Jianing Wang, Yizhong Zeng, Zhongwen Hu:
Using NOC technology to improve photoelectric encoder system for LAMOST spectroscopes. 64-66 - Zhidong Mao, Liguang Chen, Yuan Wang, Jinmei Lai:
A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain. 67-70 - Tuan Minh Phan Ho, Thang Minh Le, Khanh Duy Vu, Seiji Mochizuki, Kenichi Iwata, Keisuke Matsumoto, Hiroshi Ueda:
A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder. 71-74 - Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A two-way parallel CAVLC encoder for 4K×2K H.264/AVC. 75-78 - Yu Jin, Shinji Kimura:
Multi-stage power gating based on controlling values of logic gates. 79-82 - Weina Zhou, Yao Zou, Lin Dai, Xiaoyang Zeng:
A high speed reconfigurable face detection architecture. 83-86 - Kanwen Wang, Shuai Chen, Wei Cao, Lingli Wang, Jiarong Tong:
A coarse-grained reconfigurable computing unit. 87-90 - Sahana Swarup, Sheldon X.-D. Tan, Zao Liu, Hai Wang, Zhigang Hao, Guoyong Shi:
Battery state of charge estimation using adaptive subspace identification method. 91-94 - Jiake Wang, Jinguang Jiang, Shanshan Li, Xu Gong, Xifeng Zhou, Qingyun Li:
A new frequency compensation scheme for current-mode DC/DC converter. 95-99 - Ze-kun Zhou, Huifang Wang, Yue Shi, Xin Ming, Bo Zhang:
A high-performance PWM controller with adjustable current limit. 100-103 - Xiao Tang, Lenian He:
Capacitor-free, fast transient response CMOS low-dropout regulator with multiple-loop control. 104-107 - Yanzhao Ma, Jun Cheng, Guican Chen:
A high efficiency current mode step-up/step-down DC-DC converter with smooth transition. 108-111 - Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara:
A non-rectifier wireless power transmission system using on-chip inductor. 112-115 - Oi-Ying Wong, Hei Wong, Wing-Shan Tam, Chi-Wah Kok:
An overview of charge pumping circuits for flash memory applications. 116-119 - Peng Zhang, Fan Ye, Junyan Ren:
Class-AB CMOS buffer with floating class-AB control. 120-123 - Guoyuan Fu, H. Alan Mantooth, Jia Di:
A new topology for fully differential amplifiers that enhances their tolerance to external disturbances. 124-127 - Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara:
Double charge pump circuit with triple charge sharing clock scheme. 128-132 - Seung-Jae Choi, Young-Hyun Jun, Bai-Sun Kong:
CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction. 133-136 - Doo Hyung Woo, Ilku Nam, Joonwoo Choi:
ROIC with adaptive reset control for improving dynamic range of IR FPAs. 137-140 - Wengang Huang, Chenghe Wang, Luncai Liu, Xiaozong Huang, Guoqiang Wang:
A signal conditioner IC for inductive proximity sensors. 141-144 - Jinghao Feng, Na Yan, Hao Min:
A low-power low-noise amplifier for EEG/ECG signal recording applications. 145-148 - Tao Yin, Huanming Wu, Qisong Wu, Haigang Yang, Jiwei Jiao:
A TIA-based interface for MEMS capacitive gyroscope. 149-152 - Jian Wang, Andreas Karlsson, Joar Sohl, Magnus Pettersson, Dake Liu:
A multi-level arbitration and topology free streaming network for chip multiprocessor. 153-158 - Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song:
Design and verification of an application-specific PLD using VHDL and SystemVerilog. 159-162 - Chaochao Feng, Jinwen Li, Zhonghai Lu, Axel Jantsch, Minxuan Zhang:
Evaluation of deflection routing on various NoC topologies. 163-166 - Hongming Chen, Xiaoyuan Chen, Tie Liu, Yuhua Cheng:
ASIC implementation of an OFDM baseband transceiver for HINOC. 167-170 - Yangfan Zhou, Zhongxiang Cao, Quanliang Li, Qi Qin, Nanjian Wu:
Design of four-transistor Pixel for high speed CMOS image. 171-174 - Yuan Wen Hau, Muhammad N. Marsono, Chia Yee Ooi, Mohamed Khalil Hani:
A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip. 175-179 - Shih-Chang Chang, I-Jen Chao, Bin-Da Liu, Chun-Yueh Huang, Mei-Hwa Lee, Hung-Yin Lin:
Design of a signal processing circuit for quartz crystal microbalance biosensors. 180-183 - Jinyu Zhu, Liji Wu, Xiangmin Zhang, Chen Jia, Chun Zhang:
A low-power 433MHz transmitter for battery-less Tire Pressure Monitoring System. 184-187 - Longjun Liu, Hongbin Sun, Wenzhe Zhao, Zuoxun Hou, Jingmin Xin, Nanning Zheng:
A high performance and low cost video processing SoC for digital HDTV systems. 188-191 - Jin Huang, Jing Xie, Zhigang Mao:
A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications. 192-195 - Yang Li, Jun Han, Shuai Wang, Junbao Liu, Xiaoyang Zeng:
A NoC-based multi-core architecture for IEEE 802.11i CCMP. 196-199 - Jiayi Sheng, Liulin Zhong, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
A method of quadratic programming for mapping on NoC architecture. 200-203 - Maofei He, Jiajie Zhang, Wenhua Fan, Zhiyi Yu, Xiaoyang Zeng:
A channel estimator for LTE downlink mapped on a multi-core processor platform. 204-207 - Lian Huai, Gerald E. Sobelman, Xiaofang Zhou:
Wideband spectrum sensing using the all-phase FFT. 208-211 - Chen Chen, Yuebin Huang, Yizhi Wang, Yun Chen, Xiaoyang Zeng:
A robust frame synchronization scheme for Broadband Power-line Communication. 212-215 - Zhang Zhang, Dongge Wang, Yuteng Pan, Dan Wang, Xiaofang Zhou, Gerald E. Sobelman:
FFT implementation with Multi-operand floating point units. 216-219 - Yan Zhao, Jinyuan Zhou, Xiaofang Zhou, Gerald E. Sobelman:
General lattice wave digital filter with phase compensation scheme. 220-223 - Shouyi Yin, Jianwei Cui, Ao Luo, Leibo Liu, Shaojun Wei:
A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems. 224-227 - Jikang Xia, Lan Chen, Ying Li, Yinhao Zhou:
System modeling and analysis of the IEEE 802.15.4 physical layer design. 228-231 - Xiaoqing Wen:
Towards the next generation of low-power test technologies. 232-235 - Chong Zhang, Tsutomu Yoshihara:
Word error control algorithm through multi-reading for NAND Flash memories. 236-239 - Lei Wang, Jianhua Jiang, Yumei Zhou, Gaofeng Ren:
A new scheme for testability improvement of ECC incorporated memory. 240-243 - Bing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin:
A BIST scheme for high-speed Gain Cell eDRAM. 244-247 - Chingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang:
Variation-resilient voltage generation for SRAM weak cell testing. 248-251 - Ramin Rajaei, Mahmoud Tabandeh, Bizhan Rashidian:
Single event upset immune latch circuit design using C-element. 252-255 - Juin J. Liou, Chang Jiang, Cao Guang-Biao, Chang Gung, Feng Chia:
Challenges of electrostatic discharge (ESD) protection in emerging silicon nanowire technology. 256-258 - Kuen-Jong Lee, Alan P. Su, Long-Feng Chen, Jia-Wei Jhou, Jiff Kuo, Mark Liu:
A software/hardware co-debug platform for multi-core systems. 259-262 - Gu Cong, Chen Hong:
HV CMOS orientated variation-aware layout and robust solution. 263-266 - Yueming Yang, Heng Quan, Zewen Shi, Xiaoyang Zeng, Zhiyi Yu:
Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs. 267-270 - Arash Abtahi Forooshani, Fakhrul Zaman Rokhani:
Addressing fault tolerance in 4-PAM signaling by using block codes for on/off-chip communication. 271-274 - Peng Zhang, Yuan Wang, Song Jia, Xing Zhang:
A novel multi-finger layout strategy for GGnMOS ESD protection device. 275-278 - Byeungchul Kim, Yoon-Jong Song, Sujin Ahn, Younseon Kang, Hoon Jeong, Dongho Ahn, Seokwoo Nam, Gitae Jeong, Chilhee Chung:
Current status and future prospect of Phase Change Memory. 279-282 - Kwan-Hee Jo, Chul-Moon Jung, Kyeong-Sik Min:
Memristor models and circuits for controlling Process-VDD-Temperature variations. 283-286 - Hao Yan, Donghui Wang, Chaohuan Hou:
The design of low leakage SRAM cell with high SNM. 287-290 - Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin:
Novel RRAM programming technology for instant-on and high-security FPGAs. 291-294 - Wenbin Liu, Jinhui Wang, Wuchen Wu, Xiaohong Peng, Ligang Hou:
A study of dual-Vt configurations of an 8T SRAM cell in 45nm. 295-298 - Meng-Fan Chang, Pi-Feng Chiu, Wei-Cheng Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu:
Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM). 299-302 - Zhao-Yong Zhang, Li-Jun Zhang, Yi-Ping Zhang, Rui Feng Huang, Shou-Dao Wu, Jian-Bin Zheng:
A 55nm ultra high density two-port register file compiler with improved write replica technique. 303-306 - Ruifeng Huang, Jianbin Zheng, Lijun Zhang, Zhaoyong Zhang, Hao Wu, Yue Yu:
Word line boost and read SA PMOS compensation (SAPC) for ROM in 55nm CMOS. 307-310 - Baoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Design of a single-ended cell based 65nm 32×32b 4R2W register file. 311-314 - Hongwei Hong, Zheng Li, Qin Li, Ruizhe Wang, Charlie Hwang:
A 90 nm 16 Mb embedded phase-change memory macro with write current smoothing and enhanced write bandwidth. 315-318 - Goro Suzuki:
Separate projection and extended Cauer method for circuit reduction. 319-323 - Nobuyuki Mihara, Goro Suzuki:
VLSI interconnect delay analysis method for ramp input signal. 324-328 - Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno:
RRA-based multi-objective optimization to mitigate the worst cases of placement. 329-332 - Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye:
Numerical characterization of multi-dielectric green's function for floating random walk based capacitance extraction. 333-336 - Peng Du, Shih-Hung Weng, Xiang Hu, Chung-Kuan Cheng:
Power grid sizing via convex programming. 337-340 - Huihong Zhang, Pengjun Wang:
Polarity optimization of XNOR/OR circuit area and power based on weighted sum method. 341-344 - Lisa Piper, Jin Zhang:
Don't let the X-bugs bite: Conquer elusive X-propagation issues early! Get them before they get you! 345-348 - Menwang Xie, Duoli Zhang, Yao Li:
Meshim: A high-level performance simulation platform for three-dimensional network-on-chip. 349-352 - Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto:
Through-Silicon-Via assignment for 3D ICs. 353-356 - Jia Liu, Yuchun Ma, Ning Xu, Yu Wang:
Incremental layout optimization for NoC designs based on MILP formulation. 357-360 - Jianping Hu, Jun Wang:
Standard cell design of a low-leakage flip-flop with gate-length biasing. 361-364 - Akitoshi Matsuda, Jin Zhang:
Debugging methodology and timing analysis in CDC solution. 365-368 - Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng:
Circuit simulation using matrix exponential method. 369-372 - Haocheng Huang, Aiwu Ruan, Yongbo Liao, Jianhua Zhu, Lin Wang, Chuanyin Xiang, Ping Li:
A new event driven testbench synthesis engine for FPGA emulation. 373-376 - Xianyang Jiang, Ying Liu, Shilei Sun, Gaofeng Wang:
An improved packing tool based on a dual-output basic logic element. 377-380 - Quanquan Li, Yingke Gao, Tiejun Zhang, Chaohuan Hou:
A test approach of combining partial scan with functional testing for high performance processors. 381-384 - Chaofan Yu, Lingli Wang, Xuegong Zhou:
Automatic layout generator for embedded FPGA cores. 385-388 - Liulin Zhong, Jiayi Sheng, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Dian Zhou:
An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture. 389-392 - Xiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai:
FPGA interconnect timing library based on the statistical method. 393-396 - Suoming Pu, Bo Yu, Xuan Zou:
Robustness and performance analysis on high speed ASIC design with canonical statistical timing model. 397-400 - Meng Yang, Hongying Xu:
Optimization of mixed polarity Reed-Muller expressions based on Whole Annealing Genetic Algorithm. 401-404 - Mark P. C. Mok, Kenneth C. K. Lo, Yuzhong Jiao, Yiu Kei Li:
CPIPQ: A common platform for silicon IP qualification. 405-408 - Huang Kun, Guoxing Zhao, Yang Xu, Zuying Luo:
Comprehensive electro-thermal(ET) analysis with considering ET coupling. 409-412 - Jiawen Wang, Li Li, Hongbing Pan, Shuzhuan He, Rong Zhang:
Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm. 413-416 - Song Chen, Yuan Yao, Takeshi Yoshimura:
Mobility overlap-removal based timing-constrained scheduling. 417-420 - Xiaolin Zhang, Zhi Lin, Song Chen, Takeshi Yoshimura:
An effecient level-shifter floorplanning method for Multi-voltage design. 421-424 - Tingkai Li:
The manufacturing of Si base thin film solar cell modules. 425-429 - Xiaomeng Chen:
Challenges and strategies in advanced CMOS technology development. 430-432 - Keqiang Qian, Wen Luo, Qi Yu:
Research on electromechanical model of micro-accelerometer based on SOI technology. 433-436 - Xiaoxu Kang, Qingyun Zuo, Jiaqing Li, Chao Yuan, Yuhang Zhao:
CMOS compatible MEMs process for post interconnect single chip integration application. 437-440 - Xifeng Zhou, Jinguang Jiang, Shanshan Li:
Cascadable current-mode multifunction filter configuration using minimum number of CCTAs and grounded capacitors. 441-444 - Xiaoyu Wang, Haigang Yang, Tao Yin, Fei Liu:
A matrix approach to low-voltage low-power log-domain CMOS current-mode adjustable-bandwidth step-gain filter design. 445-448 - Luo Wang, Huihui Ji, Quan Sun:
A sigma-delta modulator with a novel chopper correlated double sampled integrator. 449-452 - Jing Li, Ran Li, Ting Yi, Zhiliang Hong, Bill Yang Liu:
VLSI implementation of high-speed low power decimation filter for LTE sigma-delta A/D converter application. 453-456 - Siliang Hua, Hao Yan, Yan Liu, Donghui Wang, Chaohuan Hou:
A continuous time sigma-delta modulator using time-domain quantizer and feedback element. 457-460 - Daehwa Paik, Masaya Miyahara, Akira Matsuzawa:
An analysis on a pseudo-differential dynamic comparator with load capacitance calibration. 461-464 - Hong Chang, Wenxian Lu, Xu Cheng, Yawei Guo, Xiaoyang Zeng:
Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications. 465-468 - Young-Hwa Kim, SeongHwan Cho:
A time-domain flash ADC immune to voltage controlled delay line non-linearity. 469-471 - Seong Jin Cho, Yohan Hong, Taegeun Yoo, Kwang-Hyun Baek:
A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array. 472-475 - Xiaojuan Li, Yintang Yang, Zhangming Zhu:
A 1.8V 100MS/s 10-bit pipelined folding A/D converter with 9.49 ENOB at Nyquist frequency. 476-479 - Haitao Wang, Hui Hong, Lingling Sun, Zhiping Yu:
A sample-and-hold circuit for 10-bit 100MS/s pipelined ADC. 480-483 - Jun Ma, Yawei Guo, Li Li, Yue Wu, Xu Cheng, Xiaoyang Zeng:
A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS. 484-487 - Hongming Chen, Xiaoyuan Chen, Yuhua Cheng:
A dual 12bit 80MSPS 3.3V Current-Steering DAC for HINOC. 488-491 - Qianqian Ha, Fan Ye, Chixiao Chen, Xiaoshi Zhu, Mingshuo Wang, Yu-Jing Lin, Ning Li, Junyan Ren:
A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. 492-495 - Guojia Liu, Lenian He, Xiaobo Xue, Qifeng Shi:
A new current switch driver with improved dynamic performance used for 500MS/s, 12-bit Nyquist current-steering DAC. 496-499 - Ran Li, Qi Zhao, Ting Yi, Zhiliang Hong:
A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS. 500-503 - Li Li, Jun Ma, Yawei Guo, Xu Cheng, Xiaoyang Zeng:
A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters. 504-507 - Akira Matsuzawa:
Energy efficient ADC design with low voltage operation. 508-511 - Yi Zhao, Jun Jiang, Ke Shao, Yajie Qin, Zhiliang Hong:
A low-power 4.224GS/s sampler in 0.13-µm CMOS for IR UWB receiver. 512-515 - Hao Zhang, Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara:
CMOS low-power subthreshold reference voltage utilizing self-biased body effect. 516-519 - Xiaozong Huang, Jing Zhang, Luncai Liu, Wengang Huang, Yanlin Zhang, Lei Yu:
A precision 2.5V bandgap voltage reference with excellent initial accuracy of 0.25% for high resolution ADCs. 520-523 - Ze-kun Zhou, Xiang-zhu Xu, Yue Shi, Xin Ming, Bo Zhang:
A high-performance bandgap reference with advanced curvature-compensation. 524-527 - Chao-Sung Lai, Tseng-Fu Lu, Jer-Chyi Wang:
Novel flash ion sensitive field effect transistor for chemical sensor applications. 528-530 - Xiaobao Chen, Zuocheng Xing, Bingcai Sui:
A model for energy quantization of single-electron transistor below 10nm. 531-534 - Xin Jiang, Ran Zhang, Takahiro Watanabe:
An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power. 535-538 - Amirali Shayan Arani, Xiang Hu, Chung-Kuan Cheng, Wenjian Yu, Christopher Pan:
Linear Dropout Regulator based power distribution design under worst loading. 539-542 - Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Tung-Yen Lai, Fu-Liang Yang:
A unipolar-CMOS with recessed source/drain load. 543-546 - Haimeng Huang, Yongwei Wang, Xingbi Chen:
An analytical model for SOI triple RESURF devices. 547-550 - Wenfang Du, Xingbi Chen:
A study of second saturation effect of OPTVLD NMOS. 551-554 - Guanghui Mei, Peicheng Li, Guangxi Hu, Ran Liu, Tingao Tang:
Quantum mechanical effects on the threshold voltage of the evenly doped surrounding-gate MOSFETs. 555-557 - S. Q. Cheng, C. J. Yao, D. M. Huang:
Effect of structural parameters on the performance and variations of nanosizes PNIN tunneling field effect transistor. 558-561 - Xiang Hu, Peng Du, Chung-Kuan Cheng:
Exploring 3D power distribution network physics. 562-565 - Rubing Bai, Shan Zeng, Qingqing Zhang, Wenjian Yu:
An efficient solver for statistical capacitance extraction considering random process variations. 566-569 - Shuang Liang, Shouyi Yin, Chongyong Yin, Leibo Liu, Shaojun Wei:
Performance evaluation modeling for reconfigurable processor. 570-573 - Riadul Islam, Seyed Ebrahim Esmaeili, Thouhidul Islam:
A high performance clock precharge SEU hardened flip-flop. 574-577 - Fengna Mei, Pengjun Wang:
Design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter. 578-581 - Jun Cheng, Sung Hoon Bang, Nak Yoon Kim, Yong Moon:
A study of frequency synthesizer for AT-DMB applications. 582-585 - Takahiro Sato, Kenichi Okada, Akira Matsuzawa:
A new figure of Merit of LC oscilators considering frequency tuning range. 586-589 - Wufeng Wang, Peichen Jiang, Tingting Mo, Jianjun Zhou:
Low noise low power two-stage modulator with injection locked LO divider in 65nm CMOS. 590-593 - Song Hu, Weinan Li, Yumei Huang, Zhiliang Hong:
Design of a low-power low-phase-noise multi-mode divider with 25%-duty-cycle outputs in 0.13µm CMOS. 594-597 - Zhuo Ma, Yang Guo, Lunguo Xie, Rongrong Liu, Hongjian Zuo:
A noise rejective VCO with build-in active LC filter. 598-601 - Xiaolu Liu, Na Yan, Xi Tan, Hao Min:
A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in 0.13µm CMOS. 602-605 - Chia-Wen Chang, Shyh-Jye Jou, Yuan-Hua Chu:
0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations. 606-609 - Ming-Chiuan Su, Shyh-Jye Jou:
Digitally-controlled cell-based oscillator with multi-phase differential outputs. 610-613 - Chen Lian, Wei Li, Haipeng Fu, Ning Li, Junyan Ren:
Low phase noise injection-locked doubler-based quadrature CMOS VCO. 614-617 - Fengjuan Wang, Zhangming Zhu, Yintang Yang, Ning Wang:
A thermal model for the top layer of 3D integrated circuits considering through silicon vias. 618-620 - Jian Lv, Yun Zhou, Baobin Liao, Yadong Jiang:
Novel high uniformity readout circuit allowing microbolometers to operate with low noise. 621-624 - Tong Ran, Guoqiang Bai:
Integration of information security chips based on System-in-Package. 625-628 - Can Wang, Qin Wang, Jianfei Jiang:
A new asynchronous delay-insensitive link based on a 1-of-4 LETS code. 629-632 - Yanfei Yang, Yintang Yang, Zhangming Zhu, Duan Zhou:
A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipeline. 633-636 - Hongqiang Zong, Jinpeng Shen, Shan Liu, Mei Jiang, Qingyuan Ban, Ling Tang, Fanyu Meng, Xin'an Wang:
An ultra low power ASK demodulator for passive UHF RFID tag. 637-640 - Shengxiao Niu, Jingjing Yang, Sheng Wang, GengSheng Chen:
Improvement and parallel implementation of canny edge detection algorithm based on GPU. 641-644 - Yiqi Wang, Fazhao Zhao, Mengxin Liu, Zhengsheng Han:
A new full current mode sense amplifier with compensation circuit. 645-648 - Zaixiao Zheng, Zhigang Mao, Jianfei Jiang:
An efficient 90nm technology-node GHz transceiver of on-chip global interconnect. 649-652 - Pei Zhang, Xiaosen Chai, Chun Xu, Jia Zhou:
Electrochemical biosensor based on modified graphene oxide for tuberculosis diagnosis. 653-656 - Ruimin Huang, Chaodong Ling, Jiaxian Wang:
Digital quadrature IF modulator using single-bit DACs. 657-660 - Yani Li, Yintang Yang, Zhangming Zhu, Wei Qiang:
Zero-crossing distortion analysis in one cycle controlled boost PFC for Low THD. 661-664 - Zhong-Fang Han, Guo-Ping Ru, Gang Ruan:
A simulation study of vertical tunnel field effect transistors. 665-668 - Xiyue Li, Wanling Deng, Junkai Huang:
Determination of the trap states distribution in Poly-Si films using the OEMS modulation. 669-672 - Xiaobo Jiang, Hongyuan Li:
High efficiency and low power multi-rate LDPC decoder design for CMMB. 673-678 - Yuan Yao, Fan Ye, Junyan Ren:
Area efficient LDPC decoder design for parallel layered decoding. 679-682 - Kai Zhang, Shuming Chen, Sheng Liu, Yaohua Wang, Junhui Huang:
Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs. 683-686 - Hao Wang, Weiguang Sheng, Weifeng He:
Automatic compilation flow for a coarse-grained reconfigurable processor. 687-690 - Yang Tang, Liu-Lin Zhong, Yu-Long Jiang:
Origin of high on-state current for dopant-segregated schottky MOSFET. 691-693 - Libo Qian, Zhangming Zhu, Yintang Yang:
System level performance evaluation of three-dimensional integrated circuit. 694-697 - Shan Cao, Zhaolin Li, Shaojun Wei:
An energy efficiency task scheduling algorithm for streaming applications on multiprocessor SoC. 698-702 - Wenjiang Liu, Yue Zhu, Tao Liu, Mengtian Rong, Hao Zhang:
Analysis and architecture design of aggregation in BM3D. 703-706 - Xun Jiang, Xiaoxin Cui, Dunshan Yu:
A JTAG-based configuration circuit applied in SerDes chip. 707-710 - Akitoshi Matsuda, Shinichi Baba:
An automated design flow for image processing filter in embedded systems. 711-714 - Huidong Zhao, Yong Hei, Shushan Qiao:
A novel channel estimation algorithm in OFDM power line communication system. 715-718 - Daying Sun, Shen Xu, Weifeng Sun, Shengli Lu, Longxing Shi:
Low power design for SoC with power management unit. 719-722 - Lidan Bao, Hongmei Wang, Tiejun Zhang, Donghui Wang, Chaohuan Hou:
Improvement on branch scheduling for VLIW architecture. 723-726 - Jianbo Xu, Zibin Dai, Yang Xuan, Yang Su:
Research on reconfigurable multiplier unit based on GF[(28)]4 field of symmetric cryptography. 727-730 - Haipeng Fu, Hanchao Zhou, Yangyang Niu, Junyan Ren, Wei Li, Ning Li:
A low-voltage differential injection locked divider with forward body bias. 731-734 - Peicheng Li, Guanghui Mei, Guangxi Hu, Ran Liu, Tingao Tang:
Effects of unintended dopants on I-V characteristics of the double-gate MOSFETs, a simulation study. 735-738 - Jun Han, Xingxing Zhang, Baoyu Xiong, Zhiyi Yu, Xiaoyang Zeng:
A control scheme for a 65nm 32×32b 4-read 2-write register file. 739-742 - Zerong Tao, Liji Wu, Xiangmin Zhang:
Reflection analysis of signal transmission in 32-bit CPU based SiP. 743-746 - Chunlin Xie, Liji Wu, Xiangmin Zhang:
Research on testing of 32-bit CPU based SiP. 747-750 - Shuai Wang, Yang Li, Junbao Liu, Jun Han, Xiaoyang Zeng:
A security processor based on MIPS 4KE architecture. 751-754 - Lei Zhang, Tao Li, Zhentao Li, Lin Jiang:
Design of a reconfigurable network interface processor. 755-759 - Tao Chen, Jiawei Zheng, Xingsi Zhang, Shengchang Cai, Yun Chen:
A hardware accelerator for speech recognition applications. 760-763 - Jun Deng, Bing Li, Lintao Liu, Rui Chen:
AProgrammable IP Core for LDPC Decoder Based onASIP. 764-767 - Jianing Su, Zhenghao Lu:
Parallel structure of GF (214) and GF (216) multipliers based on composite finite fields. 768-771 - Shanggong Feng, Yanhu Chen, Huijun Li, Minghua Zhang:
A new method to improve the unconditional stability of InGaP/GaAs heterojunction bipolar transistor. 772-774 - Jinran Du, Wanghui Zou, Xuecheng Zou:
An accurate physics-based method for calculating DC inductance of on-chip square multi-layer inductors. 775-778 - Junjuan Liu, Xi Tan, Hao Min:
Dual frequency based Real Time Location System using passive UHF RFID. 779-782 - Yucheng Liu, Jing Xie, Zhigang Mao:
A reconfigurable linear array processor architecture for data parallel and computation intensive applications. 783-786 - Shuai Chen, Jialin Chen, Kanwen Wang, Wei Cao, Lingli Wang:
A permutation network for configurable and scalable FFT processors. 787-790 - Pan Hao, Hong Qi, Du Jiaqin, Pan Pan:
Comparison of 2D MESH routing algorithm in NOC. 791-795 - Yingying Li, Guo-Ping Ru, Z.-M. Simon Li:
Simulation of carrier transport in quantum cascade lasers. 796-799 - Mengqin Xiao, Xiang Shen, Junyu Wang, Joseph Crop:
Design of a UHF RFID tag baseband with the hummingbird cryptographic engine. 800-803 - Yichao Lu, Satoshi Goto:
A study on channel polarization and polar coding. 804-807 - Jianbao Deng, Shilin Zhang, Luhong Mao, Sheng Xie, Huichao Li:
A novel linear power amplifier for 2.6GHz LTE applications. 808-811 - Zhuping Wang, Keshu Zhang:
Design of a monolithic low-power micro-sensor signal processing system. 812-815 - Ligang Hou, Shu Bai, Jinhui Wang:
TSV based 3D IC wire length calculation algorithm. 816-819 - Xiao Zhao, Huajun Fang, Jun Xu:
A new low power symmetric folded cascode amplifier by recycling current in 65nm CMOS technology. 820-823 - Tianwang Li, Jinguang Jiang, Bo Ye, Xingcheng Han:
Ultra low voltage, wide tuning range voltage controlled ring oscillator. 824-827 - Hossein Yahyatabar, Farhad Razaghian, Mehran Yahyavi, Mohsen Habib Nezhad:
A 2.5V supply low noise CMOS amplifier using noise reduction technique of Chopper stabilization. 828-833 - Gang Hu, Wenjian Yu, Hao Zhuang, Shan Zeng:
Efficient floating random walk algorithm for interconnect capacitance extraction considering multiple dielectrics. 834-837 - Xu Gong, Jinguang Jiang, Xifeng Zhou, Zhongzhi Yuan:
A dual mode high efficiency buck DC-DC converter. 838-842 - Taiyi Huang, Qihui Zhang, Weifeng Zhang:
A novel transimpedance amplifier for 10 Gbit/s optical communication system. 843-846 - Meng Yang, Gengsheng Chen:
Single event upset mitigation for FDP2008. 847-849 - Zhifu Hu, Xuebang Gao, Shujun Cai:
Electro-thermal model extraction of power GaN HEMT using I-V pulsed and DC measurements. 850-853 - Lele Jiang, Xiaojing Qin, Lifu Chang, Yuhua Cheng:
Characterization and analysis of pattern dependent variation-aware interconnects for a 65nm technology. 854-857 - Huanming Wu, Haigang Yang, Xiaoyan Cheng, Tao Yin, Jiwei Jiao:
Integrated Gm-C based PI controller for MEMS gyroscope drive loop. 858-861 - Yilei Li, Yu Wang, Na Yan, Xi Tan, Hao Min:
A subthreshold MOSFET bandgap reference with ultra-low power supply voltage. 862-865 - Hui Wang, Taotao Yan, Dongpo Chen, Jianjun Zhou:
A highly linear wideband variable gain CMOS balun-LNA. 866-869 - Miao Yang, Weifeng Sun, Shen Xu, Shengli Lu, Longxing Shi:
A 65nm 10MHz single-inductor dual-output switching buck converter with time-multiplexing control. 870-873 - Xiao Ma, Guoqiang Bai:
Design and implementation of pipelined TMVP multiplier using block recombination. 874-877 - Yani Li, Yintang Yang, Zhangming Zhu, Wei Qiang:
A novel low THD 4-quadrant analog multiplier using feedforward compensation for PFC. 878-881 - Jinguang Jiang, Qingyun Li, Xifeng Zhou:
An inductorless CMOS LNA with single input and differential output. 882-885 - Zhiyu Xu, Xinnan Lin, Hao Zhuang, Bo Jiang, Haijun Lou, Jin He:
A new nonlinear parameterized model order reduction technique combining the interpolation method and Proper Orthogonal Decomposition. 886-889 - Yilei Li, Yu Wang, Na Yan, Xi Tan, Hao Min:
A 0.6 ppm/°C current-mode bandgap with second-order temperature compensation. 890-893 - Chen Shu, Guanghua Shu, Jun Xu, Fan Ye, Junyan Ren:
A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS. 894-897 - Jiang Chen, Shilin Zhang, Luhong Mao:
A sixth-order Chebyshev low-pass filter for single-chip UHF RFID reader. 898-901 - Muwahida Liaquat, Mohammad Bilal Malik:
A realizable reconstruction filter for sampled data systems. 902-905 - Shujuan Yin, Xiangyu Li:
Optimization of ADM with both restrictions of resolution and power dissipation in low supply voltage. 906-909 - Liu Liu, Yongqiang Lu, Qiang Zhou:
A timing-perspective study on the wire model in placement. 910-913 - Weilu Su, Longzhao Shi:
Design for testability of FFT/IFFT IP core for UWB systems. 914-917 - Chao Zhang, Zhijia Yang, Zhipeng Zhang:
A CMOS hysteresis undervoltage lockout with current source inverter structure. 918-921 - Shujuan Yin:
A high linearity MOS capacitor for low voltage applications. 922-924 - Xiaojuan Li, Yintang Yang, Zhangming Zhu:
A low-kickback preamplifier with offset cancellation for pipelined folding A/D Converter. 925-928 - Haitao Han, Wen Yin, Wenqian Wang, Zegui Pang:
Auto-assign method for large scale flip-chip package design. 929-932 - Nan Zhang, Lingling Sun, Jincai Wen, Jun Liu, Jia Lou, Guodong Su, He Li:
A 60GHz power amplifier using 90-nm RF-CMOS technology. 933-936 - Xinrui Zhang, Liguang Chen, Liyun Wang, Jian Wang, Jinmei Lai:
The design and verification of SEU-hardened configurable DFF. 937-940 - Yifan Zhou, Weiguang Sheng, Xie Liu, Weifeng He, Zhigang Mao:
Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm. 941-944 - Peng Chen, Yushun Guo:
Improved algorithm for Pareto front computation for CMOS OpAmp based on multi-objective genetic optimization. 945-948 - Yongsheng Yin, Rui Zhang, Jun Yang, Minglun Gao:
Calibration method considering second-order error term of timing skew for a novel multi-channel ADC. 949-952 - Liyuan Wang, Yushun Guo:
Large-signal MOSFET modeling by means of knowledge based fuzzy logic system. 953-956 - Lulu Feng, Zibin Dai, Wei Li, Jianlei Cheng:
Design and application of reusable SoC verification platform. 957-960 - Bo Li, Liji Wu, Xiangmin Zhang:
New power rail ESD clamp design with current starving technology. 961-964 - Junwei He, Liji Wu, Xiangmin Zhang:
Design and implementation of a low Power Java Coprocessor for dual-interface IC Bank Card. 965-969 - Tianyun Zhang, Rui Zhang, Lingli Wang, Yu Hu:
A method to build reconfigurable architectures by extracting common subgraphs. 970-973 - Biye Xu, Lenian He:
A novel high-accuracy clock stabilizer with 50% duty cycle. 974-977 - Qin Wu, Wei Li, Ning Li, Junyan Ren:
A 1.2 V 70 mA low drop-out voltage regulator in 0.13 µm CMOS process. 978-981 - Ling Lin, Jianping Qiu, Lenian He:
Compensator design for digital controlled switched-mode power supplies. 982-985 - Peiyuan Wan, Wei Lang, Di Fang, Wei Cui, Pingfen Lin:
A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS. 986-989 - Dawei Fu, Lenian He, Biye Xu:
A novel RSD correction for pipeline ADC. 990-993 - Guannan Xu, Chen Jia, Chun Zhang, Zhihua Wang:
A digital sliding mode controller for switching power supply converters. 994-997 - Hao Li, Hong Zhang, Xunwei Weng, Ruizhi Zhang:
A low-power Gm-R-C image rejection filter for complex low-IF receiver. 998-1001 - Chunchen Gu, Yi Zhao, Zhiliang Hong:
A 4GS/s 3b two-way time-interleaved ADC in 0.13um CMOS. 1002-1005 - Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng:
A low power 1.0 GHz VCO in 65nm-CMOS LP-process. 1006-1009 - Changhong Huan, Xiushan Wu, Dan Wang:
A charge-pump circuit to restrain reference spurs in the PLL. 1010-1013 - Shaolong Liu, Hui Wang, Yuhua Cheng:
A wide lock-range, low jitter phase-locked loop for multi-standard SerDes application. 1014-1017 - Weibo Hu, Yen-Ting Liu, Tam Q. Nguyen, Bosco Dsouza, Donald Y. C. Lie:
Ultralow-power analog front-end IC design for an implantable cardioverter defibrillator (ICD). 1018-1021 - Kenichi Okada:
A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver. 1022-1025 - Hongliang Tian, Dongpo Chen, Tingting Mo, Jianjun Zhou:
An area-efficient dual-channel RF receiver for GPS-L1/Galileo-E1/Compass-B1. 1026-1029 - Xingli Huang, Xi Qin, Yajie Qin, Hao Fang, Zhiliang Hong:
A 0.8-3GHz 40dB dynamic range CMOS variable-gain amplifier. 1030-1033 - Haiyi Wang, Peichen Jiang, Tingting Mo, Jianjun Zhou:
A low-noise WCDMA transmitter with 25%-duty-cycle LO generator in 65nm CMOS. 1034-1037 - Yilei Li, Kefeng Han, Na Yan, Xi Tan, Hao Min:
Power amplifier driver for SDR transmitter with high gain tuning range and dynamic power control. 1038-1041 - Shaoheng Lin:
A 0.18µm CMOS 2.5Gbps pre-amplifier with AGC. 1042-1045 - Augusto Tazzoli, Matteo Rinaldi, Chengjie Zuo, Nipun Sinha, Jan Van der Spiegel, Gianluca Piazza:
Aluminum Nitride reconfigurable RF-MEMS front-ends. 1046-1049 - Chihoon Choi, Joonwoo Choi, Ilku Nam:
A low noise and highly linear 2.4-GHz RF front-end circuit for wireless sensor networks. 1050-1053 - Lijiong Wang, Tingting Mo, Dongpo Chen:
An auto-calibrating I/Q mismatch scheme for high image rejection GPS RF receiver. 1054-1057 - Renzhong Xie, Chen Jiang, Weinan Li, Yumei Huang, Zhiliang Hong:
A dual-mode analog baseband utilizing digital-assisted calibration for WCDMA/GSM receivers. 1058-1061 - Xiaobin Shen, Taotao Yan, Yuxiao Lu, Jianjun Zhou:
A 0.25dB gain step high linear programmable gain amplifier. 1062-1065 - Chen Jiang, Renzhong Xie, Weinan Li, Yumei Huang, Zhiliang Hong:
Reconfigurable low pass filter with Automatic Frequency Tuning for WCDMA and GSM application. 1066-1069 - Yu Wang, Na Yan, Hao Min:
A wide tuning range low-pass Gm-C filter for multi-mode wireless receivers with automatic frequency calibration. 1070-1073 - Feibai Zhu, Min Li, Haichao Han, Junyu Wang:
RFIDsense: A reconfigurable RFID sensor tag platform conforming to IEEE 1451.7 standard. 1074-1077 - Xiao Wang, Wenjun Sheng, Yang Li:
Directional coupler design in 3G/LTE Power Amplifier Module (invited paper). 1078-1081 - Jingyang Zhang, Dawn Wang, Hanyi Ding, John Gillis, Wan Ni, Susan L. Sweeney, Dasheng Fang:
SiGe HBT Power Amplifier design using 0.35 µm BiCMOS technology with through-silicon-via. 1082-1085 - Lin Hua, Qiong Yan, Lei Chen, Runxi Zhang, Chunqi Shi, Zongsheng Lai:
A 0.8-2.5GHz wideband SiGe BiCMOS low noise amplifier with noise fiugre of 1.98-3.3dB. 1086-1089 - Song Hu, Weinan Li, Yumei Huang, Zhiliang Hong:
Design of a high-linearity RF front-end with IP2 calibration for SAW-less WCDMA receivers. 1090-1093 - Philip Brisk:
Architecture and design automation for application-specific processors. 1094-1097 - Philippe Coussy, Dominique Heller, Cyrille Chavet:
High-Level Synthesis: On the path to ESL design. 1098-1101 - Kyle Rupnow, Yun Liang, Yinan Li, Deming Chen:
A study of high-level synthesis: Promises and challenges. 1102-1105 - Yi Ni, Wai Sum Mong, Jianwen Zhu:
On virtual prototyping of embedded system-on-chips. 1106-1109
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