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ORCIDCICC 2013: San Jose, California, USA
- Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013, San Jose, CA, USA, September 22-25, 2013. IEEE 2013
- Sakshi Arora, David K. Su, Bruce A. Wooley:
A compact 120-MHz 1.8V/1.2V dual-output DC-DC converter with digital control. 1-4 - Zhidong Liu, Hoi Lee:
A 100V gate driver with sub-nanosecond-delay capacitive-coupled level shifting and dynamic timing control for ZVS-based synchronous power converters. 1-4 - James Lin
, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa:
A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers. 1-4 - Leibo Liu, Weilong Zhang, Chenchen Deng, Shouyi Yin, Shanshan Cai, Shaojun Wei:
SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process. 1-4 - Ji-Eun Jang, Si-Jung Yang, Jaeha Kim:
Event-driven simulation of Volterra series models in SystemVerilog. 1-4 - Essam S. Atalla, Frank Zhang, Abdellatif Bellaouar, Poras T. Balsara:
Estimation of passive mixer output bandwidth using switched-capacitor techniques. 1-4 - Greg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken:
The past present and future of design-technology co-optimization. 1-8 - Nan Qi, Baoyong Chi, Yang Xu, Zhou Chen, Jun Xie, Yang Xu, Zheng Song, Zhihua Wang:
An asymmetric dual-channel reconfigurable receiver for GNSS in 180nm CMOS. 1-4 - Rune Kaald, Bjørnar Hernes, Christian Holdo, Frode Telstø, Ivar Løkken:
A 500 MS/s 76dB SNDR continuous time delta sigma modulator with 10MHz signal bandwidth in 0.18μm CMOS. 1-4 - Dennis Michael Fischette, Jaeha Kim:
Wireline transmitter and receiver design techniques. 1 - Vineet Agrawal, N. Kepler, David Kidd, Gokul Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, Taiji Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama:
Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. 1-4 - Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra:
Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics. 1-4 - Karim Boutros, Rongming Chu, Brian Hughes:
Recent advances in GaN power electronics. 1-4 - Jabeom Koo, Augusto Tazzoli, Jeronimo Segovai-Fernandez, Gianluca Piazza, Brian P. Otis:
A -173 dBc/Hz @ 1 MHz offset Colpitts oscillator using AlN contour-mode MEMS resonator. 1-4 - Jun Li, Hirohito Mukai, Mehmet Parlak, Michiaki Matsuo, James F. Buckwalter:
A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOS. 1-4 - Leibo Liu, Chenchen Deng, Dong Wang, Min Zhu, Shouyi Yin, Peng Cao, Shaojun Wei:
An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. 1-4 - David Murphy, Mohyee Mikhemar, Ahmad Mirzaei, Hooman Darabi:
Advances in the design of wideband receivers. 1-8 - Tao Zeng, Kevin Townsend, Jingbo Duan, Degang Chen:
A 15-bit binary-weighted current-steering DAC with ordered element matching. 1-4 - Hasnain Lakdawala, Eric Naviasky:
Analog techniques II. 1 - Maarten De Bock, Pieter Rombouts:
A double-sampling cross noise-coupled Sigma Delta modulator with a reduced amount of opamps. 1-4 - Srikar Bhagavatula, Byunghoo Jung:
A power sensor with 80ns response time for power management in microprocessors. 1-4 - Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong:
A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB. 1-4 - Xiaochen Yang, Robert Payne, Jin Liu:
A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs. 1-4 - Edward K. F. Lee:
An active rectifier/regulator combo circuit for powering biomedical implants. 1-4 - Don Thelen, Xicheng Jiang:
Analog techniques I. 1 - Vaibhav Tripathi, Boris Murmann:
Mismatch characterization of small metal fringe capacitors. 1-4 - Mike Peng Li, Takahiro J. Yamaguchi:
Electrical and photonic I/O test and debug. 1-2 - Wolfgang Furtner, Stephan Schacher, Markus Littow, Lionel Cimaz, Pekka E. Leinonen:
BIF - Battery interface standard for mobile devices. 1-8 - Puneet Gupta:
Design for nanoscale patterning. 1-52 - Wayne H. Woods, Alberto Valdes-Garcia, Hanyi Ding, Jay Rascoe:
CMOS millimeter wave phase shifter based on tunable transmission lines. 1-4 - Muhammad Ahmadi, Won Namgoong:
A 3.3fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocation. 1-4 - Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard:
Distributed clock generator for synchronous SoC using ADPLL network. 1-4 - Mehran Bakhshiani, Michael A. Suster, Pedram Mohseni:
A broadband biosensor interface IC for miniaturized dielectric spectroscopy from MHz to GHz. 1-4 - Igor Arsovski, Travis Hebig, John Goss, Paul Grzymkowski, Josh Patch:
Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory. 1-4 - Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull:
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation. 1-4 - Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. 1-4 - Salvatore Levantino, Carlo Samori:
Nonlinearity cancellation in digital PLLs (Invited paper). 1-8 - Jian Xu, Zhi Yang:
A 50 μW/Ch artifacts-insensitive neural recorder using frequency-shaping technique. 1-4 - Eric Naviasky, Hasnain Lakdawala:
Oversampled ADC's. 1 - Jiageng Huang, Shiliang Yang, George Jie Yuan:
A 10-MHz bandwidth 70-dB SNDR 640MS/s continuous-time ΣΔ ADC using Gm-C filter with nonlinear feedback DAC calibration. 1-4 - Hsin-Lun Li, Chia-Cheng Pao, Bo-Ming Chen, Chien-Hung Tsai:
AOT-controlled dual-mode AVP buck regulator with AEAF mechanism. 1-4 - Mihai A. T. Sanduleanu, Alberto Valdes-Garcia, Y. Liu, Benjamin D. Parker, Shlomo Shlafman, Benny Sheinman, Danny Elad, Scott K. Reynolds, Daniel J. Friedman:
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI. 1-4 - Manideep Gande, Ho-Young Lee, Hariprasath Venkatram, Jon Guerber, Un-Ku Moon:
Blind background calibration of harmonic distortion based on selective sampling. 1-4 - James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. 1-4 - Shupeng Sun, Xin Li, Chenjie Gu:
Structure-aware high-dimensional performance modeling for analog and mixed-signal circuits. 1-4 - Trevor C. Caldwell, David Alldred, Zhao Li:
A reconfigurable ΔΣ modulator with up to 100 MHz bandwidth using flash reference shuffling. 1-4 - Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Miki Tanaka, Shinji Tanaka, Koji Nii:
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. 1-4 - Naga Rajesh, Shanthi Pavan:
A lumped component programmable delay element for Ultra-Wideband beamforming. 1-4 - Brian Otis:
Low power chip & system design for biomedicai applications. 1-53 - Jean-Pierre Colinge, Sang H. Dhong:
Prospective for nanowire transistors. 1-8 - Richard A. Wachnik, Sungjae Lee, Li-Hong Pan, Ning Lu, Hongmei Li, Raphael Bingert, Mai Randall, Scott K. Springer, Christopher S. Putnam:
Gate stack resistance and limits to CMOS logic performance. 1-4 - Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu:
A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. 1-4 - Boris Murmann:
A/D converter circuit and architecture design for high-speed data communication. 1-78 - Mohammad Ranjbar, John A. McNeill:
Nyquist rate A/D converters. 1 - Yung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li:
A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching. 1-4 - Bongjin Kim, Weichao Xu, Chris H. Kim:
A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal. 1-4 - Sedigheh Hashemi, Behzad Razavi:
A 7.1-mW 1-GS/s ADC with 48-dB SNDR at Nyquist rate. 1-4 - Gerrit den Besten, Harold G. Hanson, Ranjeet K. Gupta:
Current-steering pre-emphasis transmitter with continuously tuned line terminations for optimum impedance match and maximum signal drive range. 1-4 - Jae-Won Nam, David Chiong, Mike Shuo-Wei Chen:
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS. 1-4 - Burak Çatli, Ali Nazemi, Tamer A. Ali, Siavash Fallahi, Yang Liu, Jaehyup Kim, Mohammed M. Abdul-Latif, Mahmoud Reza Ahmadi, Hassan Maarefi, Afshin Momtaz, Namik Kocaman:
A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications. 1-4 - Dandan Zhang, Haigang Yang, Zhujia Chen, Wei Li, Zhihong Huang, Lijiang Gao, Wen-rui Zhu:
A fast-locking digital DLL with a high resolution time-to-digital converter. 1-4 - Salvatore Levantino:
Advanced digital phase-locked loops. 1-95 - Siva V. Thyagarajan, Ali M. Niknejad, Christopher D. Hull:
A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOS. 1-4 - Shuai Chen, Hao Li, Liqiong Yang, Zongren Yang, Weiwu Hu, Patrick Yin Chiang:
A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS. 1-4 - Christine P. Tan, Congshu Zhou, Yi Tian, Chang Liu, Hein-Mun Lam, Jian Zhang, Mark Lu:
Design for manufacturing layout analyses correlate layout to physico-chemical yield loss mechanisms. 1-4 - Hariprasath Venkatram, Benjamin P. Hershberg, Taehwan Oh, Manideep Gande, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
Parallel gain enhancement technique for switched-capacitor circuits. 1-4 - Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada:
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. 1-4 - Man Pun Chan, Philip K. T. Mok:
A monolithic digitally controlled ripple-based DC-DC converter with digital inductor current sensor. 1-4 - Hegong Wei, Peng Zhang, Bibhudatta Sahoo, Behzad Razavi:
An 8-Bit 4-GS/s 120-mW CMOS ADC. 1-4 - Khurram Muhammad, Ming-Cho Chen, Kai-Hung Wang, Kuang-Ping Ma, Yu-Lin Hiseh, Wei-Show Hsu, Yuan-Yu Fu, Meng-Chang Lee, Shuo-Yuan Hsiao, Chih-Ming Hung:
An adaptive predistorter for wireless LAN RFSoC with embedded PA and T/R switch in 55nm CMOS. 1-4 - Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection. 1-8 - Ken Takeuchi:
Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory. 1-6 - Q. Guo, Michael A. Suster, R. Surapaneni, Carlos H. Mastrangelo, Darrin J. Young:
Design and characterization of electronic sensing system for a 13 × 13 biomechanical ground reaction sensor array. 1-4 - Koji Nii, Toshiaki Kirihata:
Advanced memory topics. 1 - Takao Nomura, Ryo Mori, Munehiro Ito, Koji Takayanagi, Toshihiko Ochiai, Kazuki Fukuoka, Kazuo Otsuga, Koji Nii, Sadayuki Morita, Tomoaki Hashimoto, Tsuyoshi Kida, Junichi Yamada, Hideki Tanaka:
Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor. 1-4 - Khaled Abdelfattah, Sherif Galal, Iuri Mehr, Alex Jianzhong Chen, Ahmet Tekin, Xicheng Jiang, Todd Brooks:
A direct-battery hookup, fully integrated stereo headphone module with 82 mW output power and 110 dB PSRR. 1-4 - Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou:
A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. 1-4 - Thomas W. Andre, Syed M. Alam, Dietmar Gogl, C. K. Subramanian, Hal Lin, W. Meadows, X. Zhang, Nicholas D. Rizzo, Jason Janesky, D. Houssameddine, Jon M. Slaughter:
ST-MRAM fundamentals, challenges, and applications. 1-8 - Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim:
A 9.2-GHz digital phase-locked loop with peaking-free transfer function. 1-4 - Hans Tuinhout:
Characterization of matching variability and low-frequency noise for mixed-signal technologies. 1-111 - X. Shawn Wang, Xin Wang, Fei Lu, Li Wang, Rui Ma, Zongyu Dong, Li Sun, Albert Z. Wang, C. Patrick Yue, Dawn Wang, Alvin J. Joseph:
A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design. 1-4 - Shunli Ma, Wei Fei, Hao Yu, Junyan Ren:
A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line. 1-4 - Matthew Loh, Azita Emami-Neyestanak:
Capacitive proximity communication with distributed alignment sensing for origami biomedical implants. 1-4 - Ephrem Wu, Khaldoon Abugharbieh, Bahareh Banijamali, Suresh Ramalingam, Paul Wu, Chris Wyland:
Interconnect and package design of a heterogeneous stacked-silicon FPGA. 1-8 - Jong Seok Park, Shouhei Kousai, Hua Wang:
A fully differential ultra-compact broadband transformer based quadrature generation scheme. 1-4 - Yue Chao, Howard C. Luong:
Transformer-based dual-band VCO and ILFD for wide-band mm-Wave LO generation. 1-4 - Maofeng Yang, Nikolas P. Papadopoulos, Czang-Ho Lee, William S. Wong, Manoj Sachdev:
A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays. 1-4 - Sang-Soo Lee, Edward Boling, Augustine Kuo, Robert Rogenmoser:
A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications. 1-4 - Min-Chie Jeng, Cheng Hsiao, Ke-Wei Su, Chung-Kai Lin:
Circuit reliability simulation using TMI2. 1-7 - Yousr Ismail, Chang-Jin Kim, Chih-Kong Ken Yang:
A bipolar >40-V driver in 45-nm SOI CMOS technology. 1-4 - Chih-Hung Chen, David Chen, Ryan Lee, Peiming Lei, Daniel Wan:
Thermal noise modeling of nano-scale MOSFETs for mixed-signal and RF applications. 1-8 - Xuan Zhang, Tao Tong, David M. Brooks, Gu-Yeon Wei:
Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOS. 1-4 - Anatoly Yakovlev, Jihoon Jang, Daniel Pivonka, Ada S. Y. Poon:
A 11μW Sub-pJ/bit reconfigurable transceiver for mm-sized wireless implants. 1-4 - Bharan Giridhar, Matthew Fojtik, David Fick, Dennis Sylvester, David T. Blaauw:
Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating. 1-4 - Andrea Mazzanti, Earl W. McCune Jr.:
RF building blocks. 1 - Alvin Li, Shiyuan Zheng, Jun Yin, Howard C. Luong, Xun Luo:
A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliers. 1-4 - Yida Duan, Elad Alon:
A 12.8GS/s time-interleaved SAR ADC with 25GHz 3dB ERBW and 4.6b ENOB. 1-4 - Gaurav Bawa, Alex Q. Huang:
Switched-capacitor filter based Type-III compensation for switched-mode Buck converters. 1-4 - Sherif H. Abdelhalem, Prasad S. Gudem, Lawrence E. Larson:
Hybrid transformer-based tunable integrated duplexer with antenna impedance tracking loop. 1-4 - Seokhyeon Jeong, Jae-Yoon Sim, David T. Blaauw, Dennis Sylvester:
65nW CMOS temperature sensor for ultra-low power microsystems. 1-4 - Dongkyung Park, Hoi Lee:
A 40V 10W 93%-efficiency current-accuracy-enhanced dimmable LED driver with adaptive timing difference compensation for solid-state lighting applications. 1-4 - Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici:
FireBird: PowerPC e200 based SoC for high temperature operation. 1-4 - Behzad Razavi:
Charge steering: A low-power design paradigm. 1-8 - Li Wang, Xin Wang, Zitao Shi, Rui Ma, Chen Zhang, Zongyu Dong, Fei Lu, Hui Zhao, Albert Z. Wang:
Scalable behavior modeling for 3D field-programmable ESD protection structures. 1-4 - Swaroop Ghosh:
Energy centric model of SRAM write operation for improved energy and error rates. 1-4 - Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS. 1-4 - Mezyad Amourah, Sandeep Krishnegowda, Morgan Whately:
A novel OTA-based fast lock PLL. 1-4 - Moongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim:
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. 1-4 - Mike Peng Li, Masashi Shimanouchi, Hsinho Wu:
Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013). 1-8 - Christoph Sandner, Rajeevan Amirtharajah:
Power management. 1 - Ashkan Borna, Yanjie Wang, Chris Hull, Hua Wang, Ali M. Niknejad:
A fully integrated highly linear receiver with automatic IP2 calibration schemes for multi-standard applications. 1-4 - Guanhua Wang, Yun Chiu:
Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering. 1-4 - Albert Z. Wang:
Concurrent design of ESD protection and ICs for optimization and prediction. 1-34 - Trent McConaghy, Brian Chen:
Variation and analog modeling. 1 - Richard Schenker, Vivek Singh:
Foundations for scaling beyond 14nm. 1-4