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ORCIDISSCC 2022: San Francisco, CA, USA
- IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022. IEEE 2022, ISBN 978-1-6654-2800-2
- Dong Yan, Dongsheng Brian Ma:
A Monolithic GaN Direct 48V/1V AHB Switching Power IC with Auto-Lock Auto-Break Level Shifting, Self-Bootstrapped Hybrid Gate Driving, and On-Die Temperature Sensing. 1-3 - Xiaofei Ma, Yan Lu, Wing-Hung Ki
:
A 27W D2D Wireless Power Transfer System with Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control. 1-3 - Yuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim:
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems. 1-3 - Yukun Zhu, Pranith R. Byreddy, Shenggang Dong, Kenneth K. O, Wooyeol Choi:
A 430GHz CMOS Concurrent Transceiver Pixel Array for High Angular Resolution Reflection-Mode Active Imaging. 1-3 - Nathan M. Monroe, Georgios C. Doqiamis, Robert Stingel, Preston Myers, Xibi Chen, Ruonan Han:
Electronic THz Pencil Beam Forming and 2D Steering for High Angular-Resolution Operation: A 98×98-Unit 265GHz CMOS Reflectarray with In-Unit Digital Beam Shaping and Squint Correction. 1-3 - Shihkai Kuo, Manideep Dunna, Dinesh Bharadia, Patrick P. Mercier:
A WiFi and Bluetooth Backscattering Combo Chip Featuring Beam Steering via a Fully-Reflective Phased-Controlled Multi-Antenna Termination Technique Enabling Operation Over 56 Meters. 1-3 - Alessandro Franceschin, Domenico Riccardi, Andrea Mazzanti:
Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM. 1-3 - Brian T. Vanderpool, Phillip J. Restle, Eric J. Fluhr, Gregory S. Still, Frank Campisano, Ian Carmichael, Eric Marz, Rahul Batra, Richard L. Willaman:
Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor. 1-3 - Haoyi Zhao, Fa Foster Dai:
A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment. 1-3 - Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. 1-3 - Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi:
A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator. 1-3 - Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi-Ren Chen, Chung-Chuan Lo, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh:
A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. 1-3 - Tingxu Hu, Mo Huang, Yan Lu, Rui Paulo Martins:
A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2x Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD. 1-3 - Win-San Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, Tung-Yin Lee, Meng-Fan Chang:
A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices. 1-3 - Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. 1-3 - Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim:
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. 1-3 - Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski:
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. 1-3 - Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques Christophe Rudell, Visvesh S. Sathe:
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. 1-3 - Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang:
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction. 1-3 - Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian Piedrahita Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst:
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. 1-3 - Seong Ju Lee, Kyu-Young Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dong Yoon Ka, Kyu-Dong Hwang, Jeongje Park, Kyeong Pil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Jaewook Lee, Donguc Ko, Younggun Jun, Keewon Cho, Ilwoong Kim, Choungki Song, Chunseok Jeong, Dae-Han Kwon, Jieun Jang, Il Park, Junhyun Chun, Joohwan Cho:
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. 1-3 - Li-Qun Weng, Li-De Chen, Hao-Chien Cheng, An-You Zheng, Kai-Ping Lin, Chao-Tsung Huang:
A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display. 1-3 - Ippei Akita, Takeshi Kawano, Hitoshi Aoyama, Shunichi Tatematsu, Masakazu Hioki:
A 2.6mW 10pTI √ Hz 33kHz Magnetoimpedance-Based Magnetometer with Automatic Loop-Gain and Bandwidth Enhancement. 1-3 - Hyojun Kim, Hyeong-Seok Oh, Woosong Jung, Yoonho Song, Jonghyun Oh, Deog-Kyoon Jeong:
A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration. 1-3 - Gérard Billiot, Paul Mattei, Bogdan Vysotskyi, Adrien Reynaud, Louis Hutin, Christophe Plantier, Emmanuel Rolland, Marc Gely, Giulia Usai, Claude Tabone, Gaël Pillonnet, Stéphanie Robinet, Sébastien Hentz:
1024 3D-Stacked Monolithic NEMS Array with 375μm20.5mW 0.28ppm Frequency Deviation Pixel-level Readout for Zeptogram Gravimetric Sensing. 1-3 - Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. 1-3 - Yuhao Ju, Jie Gu:
A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance. 1-3 - Li Xu, Maya Lassiter, Xiao Wu, Yejoong Kim, Jungho Lee, Makoto Yasuda, Masaru Kawaminami, Marc Miskin, David T. Blaauw, Dennis Sylvester:
A 210×340×50µm Integrated CMOS System f0r Micro-Robots with Energy Harvesting, Sensing, Processing, Communication and Actuation. 1-3 - Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. 1-3 - David Joseph Munzer, Naga Sasikanth Mannem, Edgar Felipe Garay, Hua Wang:
A Broadband Mm-Wave VSWR-Resilient Joint True-Power Detector and Impedance Sensor Supporting Single-Ended Antenna Interfaces. 1-3 - Henry Hinton, Houk Jang, Wenxuan Wu, Min-Hyun Lee, Minsu Seol, Hyeon-Jin Shin, Seongjun Park, Donhee Ham:
A 200 x 256 Image Sensor Heterogeneously Integrating a 2D Nanomaterial-Based Photo-FET Array and CMOS Time-to-Digital Converters. 1-3 - Jiang Gong, Bishnu Patra, Luc Enthoven, Job van Staveren, Fabio Sebastiano, Masoud Babaie:
A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FoMA in 22nm FinFET. 1-3 - Shuo Li, Xinjian Liu, Benton H. Calhoun:
A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy-Harvesting and Power-Management Platform with 1.2×105 Dynamic Range, Integrated MPPT, and Multi-Modal Cold Start-Up. 1-3 - Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei, Shouyi Yin:
A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing. 1-3 - Drew A. Hall, Nagaraj Ananthapad Manabhan, Chulmin Choi, Le Zheng, Paul P. Pan, Carl W. Fuller, Pius P. Padayatti, Calvin Gardner, Daniel Gebhardt, Zsolt Majzik, Prem Sinha, Paul W. Mola, Barry Merriman:
A CMOS Molecular Electronics Chip for Single-Molecule Biosensing. 1-3 - Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie:
184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. 1-3 - Huajun Zhang, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan:
A 121.4dB DR, -109.8dB THD+N Capacitively-Coupled Chopper Class-D Audio Amplifier. 1-3 - Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu:
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. 1-3 - Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. 1-3 - Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang:
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. 1-3 - Harijot Singh Bindra, Jeroen Ponte, Bram Nauta:
A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch. 1-3 - Cameron Hill, James F. Buckwalter:
A 1-to-18GHz Distributed-Stacked-Complementary Triple-Balanced Passive Mixer With up to 33dBm IIP3 and Integrated LO Driver in 45nm CMOS SOI. 1-3 - Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura:
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. 1-3 - Sangwoo Kim, Taehyoung Kim, Kiwon Seo, Gunhee Han:
A Fully Digital Time-Mode CMOS Image Sensor with 22.9pJ/frame.pixel and 92dB Dynamic Range. 1-3 - Zhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, Yangtao Dong, Ting Guo:
A 0.0078mm2 3.4mW Wideband Positive-feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting Gm Boosting. 1-3 - Xinjian Liu, Sumanth Kamineni, Jacob Breiholz, Benton H. Calhoun, Shuo Li:
A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization. 1-3 - Shoubhik Karmakar, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan:
A -91 dB THD+N Resistor-Less Class-D Piezoelectric Speaker Driver Using a Dual Voltage/ Current Feedback for LC Resonance Damping. 1-3 - Kyu-Jin Choi, Jae-Yoon Sim:
A Time-Division Multiplexed 8-Channel Non-Contact ECG Recording IC with a Common-Mode Interference Tolerance of 20VPP. 1-3 - Chuan-Yi Wu, Chi-Wei Liu, Jing-Siang Chen, Cong-Sheng Huang, Ting-Heng Lu, Ling-Chia Chen, I-Che Ou, Sook-Kuan Lee, Yen-Chi Chen, Po-Hung Chen, Chi-Te Liu, Ying-Chih Liao, Yu-Te Liao:
A Self-powering Wireless Soil-pH and Electrical Conductance Monitoring IC with Hybrid Microbial Electrochemical and Photovoltaic Energy Harvesting. 1-3 - Changuk Lee, Byeongseol Kim, Jejung Kim, Sangwon Lee, Taejune Jeon, Woojun Choi, Sunggu Yang, Jong-Hyun Ahn, Joonsung Bae, Youngcheol Chae:
A Miniaturized Wireless Neural Implant with Body-Coupled Data Transmission and Power Delivery for Freely Behaving Animals. 1-3 - Ha-Il Song, Hanho Choi, Jun Young Yoo, Hyosup Won, Cheong Min Lee, Huxian Jin, Tai Young Kim, Woohyun Kwon, Kyoohyun Lim, Konan Kwon, Chang-Ahn Kim, Taeho Kim, Jun-Gi Jo, Jake Eu, Sean Park, Hyeon-Min Bae:
A 50Gb/s PAM-4 Bi-Directional Plastic Waveguide Link with Carrier Synchronization Using PI-Based Costas Loop. 1-3 - Chan Sam Park, Hyunjoong Kim, Kwangmuk Lee, Dae Sik Keum, Dong Pyo Jang, Jae Joon Kim:
A 145.2dB-DR Baseline-Tracking Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular Monitoring. 1-3 - Bahram Zand, Mike Bichan, Alireza Mahmoodi, Mansour Shashaani, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Eric Liu, Nima Soltani, Al Freeman, Rishi Anand, Syed Rubab, Ranjit Khela, Shaham Sharifian, Karl Herterich:
A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm. 1-3 - Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun:
A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR. 1-3 - Sungbong Park, Changkyu Lee, Sangcheon Park, Haeyong Park, Taeheon Lee, Dami Park, Minsung Heo, Inyong Park, Hyunyoung Yeo, Youna Lee, Juhee Lee, Beomsuk Lee, Dong-Chul Lee, Jinyoung Kim, Bokwon Kim, Jinsun Pyo, Shili Quan, Sungyong You, Inho Ro, Sungsoo Choi, SungIn Kim, Insung Joe, Jongeun Park, Chang-Hyo Koo, Jae-Ho Kim, Chong Kwang Chang, Taehee Kim, JinGyun Kim, Jamie Lee, Hyunchul Kim, Changrok Moon, Hyoung-Sub Kim:
A 64Mpixel CMOS Image Sensor with 0.50µm Unit Pixels Separated by Front Deep-Trench Isolation. 1-3 - Junyao Tang, Lei Zhao, Cheng Huang:
A 68.3% Efficiency Reconfigurable 400-/800-mW Capacitive Isolated DC-DC Converter with Common-Mode Transient Immunity and Fast Dynamic Response by Through-Power-Link Hysteretic Control. 1-3 - Jeong-Hyun Cho, Dong-Kyu Kim, Hong-Hyun Bae, Yong-Jin Lee, Seok-Tae Koh, Young-Hwan Choo, Ji-Seon Paek, Hyun-Sik Kim:
A 1.23W/mm2 83.7%-Efficiency 400MHz 6-Phase Fully Integrated Buck Converter in 28nm CMOS with On-Chip Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/ns. 1-3 - Jingyi Yuan, Zeguo Liu, Feng Wu, Lin Cheng:
A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9µS 1% Settling Time for a 3A/20ns Load Transient. 1-3 - Ted Pekny, Luyen Vu, Jeff Tsai, Dheeraj Srinivasan, Erwin Yu, Jonathan Pabustan, Joe Xu, Srinivas Deshmukh, Kim-Fung Chan, Michael Piccardi, Kevin Xu, Guan Wang, Kaveh Shakeri, Vipul Patel, Tomoko Iwasaki, Tongji Wang, Padma Musunuri, Carl Gu, Ali Mohammadzadeh, Ali Ghalam, Violante Moschiano, Tommaso Vali, Jae-Kwan Park, June Lee, Ramin Ghodsi:
A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array. 1-3 - Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim:
A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces. 1-3 - Kwantae Kim, Chang Gao, Rui Graça, Ilya Kiselev, Hoi-Jun Yoo, Tobi Delbrück, Shih-Chii Liu:
A 23μW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature Extraction. 1-3 - Chen Chen, Jin Liu, Hoi Lee:
A 2-5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR Boosting Scheme Achievi 1 ng 91% Efficie 1 ncy at a Conversion Ratio of 12. 1-3 - Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Steven K. Hsu, Amit Agarwal, Vivek K. De, Sanu K. Mathew:
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS. 1-3 - Onur Memioglu, Yu Zhao, Behzad Razavi:
A 300GHz 52mW CMOS Receiver with On-Chip LO Generation. 1-3 - George Zettles, Scott Willenborg, Blake R. Johnson, Andrew Wack, Brian Allison:
26.2 Design Considerations for Superconducting Quantum Systems. 1-3 - Thomas Burd, Wilson Li, James Pistole, Srividhya Venkataraman, Michael McCabe, Timothy Johnson, James Vinh, Thomas Yiu, Mark Wasio, Hon-Hin Wong, Daryl Lieu, Jonathan White, Benjamin Munger, Joshua Lindner, Javin Olson, Steven Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar:
Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core. 1-3 - Sam Razavian, Aydin Babakhani:
A Highly Power Efficient 2×3 PIN-Diode-Based Intercoupled THz Radiating Array at 425GHz with 18.1dBm EIRP in 90nm SiGe BiCMOS. 1-3 - Luya Zhang, Ali M. Niknejad:
A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1 dB FoM Using a Proportionally Divided Charge Pump. 1-3 - Charlotte Frenkel, Giacomo Indiveri:
ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales. 1-3 - Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. 1-3 - Christopher Schaef, Tamir Salus, Rachid Rayess, Siddarth Kulasekaran, Mat Manusharow, Kaladhar Radhakrishnan, Jonathan Douglas:
A IMax |max, Fully Integrated Multi-Phase Voltage Regulator with 91.5% Peak Efficiency at 1.8 to 1V, Operating at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOS. 1-3 - Jun-Suk Bang, Dong-Su Kim, Jeongkwang Lee, Sung-Youb Jung, Young-Hwan Choo, Seungchan Park, Young-Ho Jung, Jae-Young Ko, Takahiro Norniyama, Jongbeom Baek, Jae-Yeol Han, Sang-Han Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho:
2-Tx Digital Envelope-Tracking Supply Modulator Achieving 200MHz Channel Bandwidth and 93.6% Efficiency for 2G/3G/LTE/NR RF Power Amplifiers. 1-3 - Youngwoo Ji, Jiawei Liao, Sina Arjmandpour, Alessandro Novello, Jae-Yoon Sim, Taekwang Jang:
A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range. 1-3 - Yu Zhao, Onur Memioglu, Behzad Razavi:
A 56GHz 23mW Fractional-N PLL with 110fs Jitter. 1-3 - Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho:
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter. 1-3 - Ashutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang Won Son, Thomas Byunghak Cho:
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. 1-3 - Christoph Rindfleisch, Bernhard Wicht:
A 110V/230V 0.3W Offline Chip-Scale Power Supply with Integrated Active Zero-Crossing Buffer and Voltage-Interval-Based Dual-Mode Control. 1-3 - Arthur Campos de Oliveira, Sining Pan, Kofi A. A. Makinwa:
A MEMS Coriolis-Based Mass-Flow-to-Digital Converter with 100µg/h/√Hz Noise i Floor and Zero Stability of ±0.35mg/h. 1-3 - Qiang Fang, Longyang Lin, Yao Zu Wong, Hui Zhang, Massimo Alioto:
Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching. 1-3 - Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS. 1-3 - Amit Kumar Mishra, Yifei Li, Pawan Agarwal, Sudip Shekhar:
A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process. 1-3 - Aart De Geus:
Catalyzing the Impossible: Silicon, Software, and Smarts for the SysMoore Era. 10-16 - Marco Cassis:
Intelligent Sensing: Enabling the Next "Automation Age". 17-24 - Inyup Kang:
The Art of Scaling: Distributed and Connected to Sustain the Golden Age of Computation. 25-31 - Renee James:
The Future of the High-Performance Semiconductor Industry and Design. 32-35 - Wilfred Gomes, Altug Koker, Patrick N. Stover, Doug B. Ingerly, Scott Siers, Srikrishnan Venkataraman, Chris Pelto, Tejas Shah, Amreesh Rao, Frank O'Mahony, Eric Karl, Lance Cheney, Iqbal Rajwani, Hemant Jain, Ryan Cortez, Arun Chandrasekhar, Basavaraj Kanthi, Raja Koduri:
Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing. 42-44 - Nevine Nassif, Ashley O. Munch, Carleton L. Molnar, Gerald Pasdast, Sitaraman V. Lyer, Zibing Yang, Oscar Mendoza, Mark Huddart, Srikrishnan Venkataraman, Sireesha Kandula, Rafi Marom, Alexandra M. Kern, William J. Bowhill, David R. Mulvihill, Srikanth Nimmagadda, Varma Kalidindi, Jonathan Krause, Mohammad M. Haq, Roopali Sharma, Kevin Duda:
Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor. 44-46 - Ofer Geva, Christopher J. Berry, Robert J. Sonnelitter, David Wolpert, Adam Collura, Thomas Strach, Di Phan, Cédric Lichtenau, Alper Buyuktosunoglu, Hubert Harrer, Jeffrey A. Zitz, Chad Marquart, Douglas Malone, Tobias Webel, Adam Jatkowski, John Isakson, Dina Hamid, Mark Cichanowski, Michael Romain, Faisal Hasan, Kevin Williams, Jesse Surprise, Chris Cavitt, Mark Cohen:
IBM Telum: a 16-Core 5+ GHz DCM. 46-48 - Rahul M. Rao, Christopher J. Gonzalez, Eric Fluhr, Abraham Mathews, Andrew Bianchi, Daniel Dreps, David Wolpert, Eric Lai, Gerald Strevig, Glen A. Wiedemeier, Philipp Salz, Ryan Kruse:
POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. 48-50 - Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang:
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. 50-52 - Uneeb Rathore, Sumeet Singh Nagi, Subramanian S. Iyer, Dejan Markovic:
A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration. 52-54 - Jaehong Jung, Seunghyun Oh, Joo-Myoung Kim, Gihyeok Ha, Jinhyeon Lee, Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seungyong Bae, Wonkang Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee, Thomas Byunghak Cho:
A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration. 58-60 - Jaehong Jung, Seungjin Kim, Wonkang Kim, Jae-Yeol Han, Euiyoung Park, Seongwook Hwang, Seunghyun Oh, Sangwook Han, Kyungsoo Lee, Junho Huh, Jongwoo Lee:
A 52MHz -158.2dBc/Hz PN @ 100kHz Digitally Controlled Crystal Oscillator Utilizing a Capacitive-Load-Dependent Dynamic Feedback Resistor in 28nm CMOS. 60-62 - Zhong Tang, Roger Zarnparette, Yoshikazu Furuta, Tomohiro Nezuka, Kofi A. A. Makinwa:
A ±25A Versatile Shunt-Based Current Sensor with 10kHz Bandwidth and ±0.25% Gain Error from -40°C to 85°C Using 2-Current Calibration. 66-68 - Bo Wang, Man-Kay Law, Amine Bermak:
A BJT-Based CMOS Temperature Sensor Achieving an Inaccuracy of ±0.45°C(3σ) from °50°C to 180°C and a Resolution-FoM of 7.2pJ.K2 at 150°C. 72-74 - Mohamed Elkhouly, Jaegeun Ha, Michael J. Holyoak, David Hendry, Mustafa Sayginer, Ryan Enright, Ioannis Kimionis, Yves Baeyens, Shahriar Shahramian:
Fully Integrated 2D Scalable TX/RX Chipset for D-Band Phased-Array-on-Glass Modules. 76-78 - Steven Callender, Amy Whitcombe, Abhishek Agrawal, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Mark Chakravorti, Stefano Pellerano, Christopher D. Hull:
A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology. 78-80