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"Memory fartitioning-based modulo scheduling for high-level synthesis."

Tianyi Lu et al. (2017)

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DOI: 10.1109/ISCAS.2017.8050969

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

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  dblp key:
  - conf/iscas/LuYYXLW17
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  - https://dblp.org/rec/conf/iscas/LuYYXLW17
Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:
Memory fartitioning-based modulo scheduling for high-level synthesis. ISCAS 2017: 1-4

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