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ORCID"A wide-range delay-locked loop with a fixed latency of one clock cycle."
Hsiang-Hui Chang et al. (2002)
- Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu:
A wide-range delay-locked loop with a fixed latency of one clock cycle. IEEE J. Solid State Circuits 37(8): 1021-1027 (2002)
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