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ORCIDIEEE Transactions on Circuits and Systems - Part II: Express Briefs, Volume 56-II
Volume 56-II, Number 1, January 2009
- Metin Sengül
:
Construction of Lossless Ladder Networks With Simple Lumped Elements Connected Via Commensurate Transmission Lines. 1-5 - Young-Suk Seo, Jang-Woo Lee, Hong-Jung Kim, Changsik Yoo, Jae-Jin Lee, Chun-Seok Jeong:
A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology. 6-10 - Joung-Yeal Kim, Young-Hyun Jun, Bai-Sun Kong:
CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction. 11-15 - Luis Hernández, Enrique Prefasi, Ernesto Pun, Susana Patón:
A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer. 16-20 - Jabeom Koo, Sunghwa Ok, Chulwoo Kim:
A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock. 21-25 - Poki Chen, Ting-Chun Liu:
Switching Schemes for Reducing Capacitor Mismatch Sensitivity of Quasi-Passive Cyclic DAC. 26-30 - Xiaojun Ma, Fabrizio Lombardi:
On the Computational Complexity of Tile Set Synthesis for DNA Self-Assembly. 31-35 - Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan:
Self-Biased Unity-Gain Buffers With Low Gain Error. 36-40 - Antonio Jesús Torralba Silgado, Clara Isabel Luján-Martínez, Ramón González Carvajal, Juan Antonio Gómez Galán, Melita Pennisi, Jaime Ramírez-Angulo, Antonio J. López-Martín:
Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques. 41-45 - Laurent-Stéphane Didier, Pierre-Yves Rivaille:
A Generalization of a Fast RNS Conversion for a New 4-Modulus Base. 46-50 - Pei-Yin Chen, Chien-Chuan Huang, Yeu-Horng Shiau, Yao-Tung Chen:
A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images. 51-55 - Jaehoon Song, Juhee Han, Hyunbean Yi, Taejin Jung, Sungju Park:
Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults. 56-60 - Leena Vachhani, K. Sridharan, Pramod Kumar Meher:
Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation. 61-65 - Tiebao Yang, Xiang Chen:
Local Robustness of Hopf Bifurcation Stabilization. 66-70 - Guoliang Wei, Zidong Wang, Xiao He, Huisheng Shu:
Filtering for Networked Stochastic Time-Delay Systems With Sector Nonlinearity. 71-75 - Francesco Amato, Carlo Cosentino, Antonino S. Fiorillo, Alessio Merola:
Stabilization of Bilinear Systems Via Linear State-Feedback Control. 76-80 - Ji-Hoon Kim, In-Cheol Park:
Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes. 81-85 - Imtinan Elahi, Khurram Muhammad, Poras T. Balsara:
Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation. 86-90
Volume 56-II, Number 2, February 2009
- Juan Pablo Alegre, Santiago Celma, Belén Calvo, Norbert Fiebig, S. Halder:
SiGe Analog AGC Circuit for an 802.11a WLAN Direct Conversion Receiver. 93-96 - Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu:
A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology. 97-101 - Miguel Ángel Gutiérrez de Anda, Arturo Sarmiento-Reyes, Luis Hernández-Martínez, Jacek Piskorowski, Roman Kaszynski:
The Reduction of the Duration of the Transient Response in a Class of Continuous-Time LTV Filters. 102-106 - Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, Shen-Iuan Liu:
A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier. 107-111 - Zhipeng Ye, Michael Peter Kennedy:
Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part II: SQ-DDSM. 112-116 - Xiang Gao, Eric A. M. Klumperink, Paul F. J. Geraedts, Bram Nauta:
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops. 117-121 - Ying-Khai Teh, Faisal Mohd-Yasin, Florence Choong, Mamun Bin Ibne Reaz, Albert Victor Kordesch:
Design and Analysis of UHF Micropower CMOS DTMOST Rectifiers. 122-126 - Armin Tajalli, Massimo Alioto, Yusuf Leblebici:
Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. 127-131 - Owen Casha, Ivan Grech, Franck Badets, Dominique Morche, Joseph Micallef:
Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers. 132-136 - Da-Huei Lee, Tai-Haur Kuo, Kow-Liang Wen:
Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method. 137-141 - Wei-Ming Lin, Shen-Iuan Liu, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu:
A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology. 142-146 - Gerrit Groenewold:
Optimal Ladder Filters. 147-151 - Feng Luo, Dongsheng Ma:
An Integrated Switching DC-DC Converter With Dual-Mode Pulse-Train/PWM Control. 152-156 - Jaehoon Jeong, Robert Nevels:
Time-Domain Analysis of a Lossy Nonuniform Transmission Line. 157-161 - Paolo Maffezzoni, Dario D'Amore:
Compact Electrothermal Macromodeling of Photovoltaic Modules. 162-166 - Behrooz Parhami:
Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters. 167-171 - Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello:
Designing High-Speed Adders in Power-Constrained Environments. 172-176 - Giovanni Russo, Mario di Bernardo:
Contraction Theory and Master Stability Function: Linking Two Approaches to Study Synchronization of Complex Networks. 177-181
Volume 56-II, Number 3, March 2009
- Kambiz K. Moez, Mohamed I. Elmasry:
A New Loss Compensation Technique for CMOS Distributed Amplifiers. 185-189 - Paul T. M. van Zeijl, Manel Collados:
On the Attenuation of DAC Aliases Through Multiphase Clocking. 190-194 - Fredrik Jonsson, Håkan K. Olsson:
A Low-Leakage Open-Loop Frequency Synthesizer Allowing Small-Area On-Chip Loop Filter. 195-199 - Shengxi Diao, Yuanjin Zheng, Chun-Huat Heng:
A CMOS Ultra Low-Power and Highly Efficient UWB-IR Transmitter for WPAN Applications. 200-204 - Jaeha Kim:
Adaptive-Bandwidth Phase-Locked Loop With Continuous Background Frequency Calibration. 205-209 - Kyoung-Sik Seol, Young-Jin Woo, Gyu-Hyeong Cho, Gyu-Ha Cho, Jae-Woo Lee:
A Synchronous Multioutput Step-Up/Down DC-DC Converter With Return Current Control. 210-214 - Jun Lin, Zhongfeng Wang, Li Li, Jin Sha, Minglun Gao:
Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders. 215-219 - Yun-Da Huang, Soo-Chang Pei, Jong-Jy Shyu:
WLS Design of Variable Fractional-Delay FIR Filters Using Coefficient Relationship. 220-224 - Xiangjun Li, Xinghuo Yu, Changhong Wang, Bingo Wing-Kuen Ling:
Periodic Input Response of a Second-Order Digital Filter With Two's Complement Arithmetic. 225-229 - Jianlong Zou, Xikui Ma, Changqing Du:
Asymmetrical Oscillations in Digitally Controlled Power-Factor-Correction Boost Converters. 230-234 - Yingying Wu, Wei Wei, Guoyang Li, Ji Xiang:
Pinning Control of Uncertain Complex Networks to a Homogeneous Orbit. 235-239 - Changchun Hua, Peter X. Liu:
Convergence Analysis of Teleoperation Systems With Unsymmetric Time-Varying Delays. 240-244 - Zheng Wang, K. T. Chau:
Design, Analysis, and Experimentation of Chaotic Permanent Magnet DC Motor Drives for Electric Compaction. 245-249 - Chengde Zheng, Huaguang Zhang, Zhanshan Wang:
New Delay-Dependent Global Exponential Stability Criterion for Cellular-Type Neural Networks With Time-Varying Delays. 250-254 - Zehui Mao, Bin Jiang, Peng Shi:
Protocol and Fault Detection Design for Nonlinear Networked Control Systems. 255-259 - Tso-Bing Juang, Ming-Yu Tsai, Chin-Chieh Chiu:
Corrections to "VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection" [Sep 08 897-901]. 260-261
Volume 56-II, Number 4, April 2009
- Kyung-Hoon Lim, Gunhyun Ahn, Sung-Chan Jung, Hyun-Chul Park, Min-Su Kim, Ju-Ho Van, Hanjin Cho, Jonghyuk Jeong, Cheon-Seok Park, Youngoo Yang:
A 60-W Multicarrier WCDMA Power Amplifier Using an RF Predistorter. 265-269 - Chia-Yu Yao, Chih-Chun Hsieh:
Hardware Simplification to the Delta Path in a MASH 111 Delta-Sigma Modulator. 270-274 - Baoyong Chi, Jinke Yao, Patrick Chiang, Zhihua Wang:
A Fast-Settling Wideband-IF ASK Baseband Circuit for a Wireless Endoscope Capsule. 275-279 - Manuel Carrasco-Robles, Luis Serrano:
A Novel Minimum-Size Activation Function and Its Derivative. 280-284 - Amit Acharyya, Koushik Maharatna, Bashir M. Al-Hashimi, Steve R. Gunn:
Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry. 285-289 - Guangming Shi, Weifeng Liu, Li Zhang, Fu Li:
An Efficient Folded Architecture for Lifting-Based Discrete Wavelet Transform. 290-294 - Vineet Agarwal, Jin Sun, Janet Meiling Wang:
Delay Uncertainty Reduction by Gate Splitting. 295-299 - Timothy M. Hollis:
Data Bus Inversion in High-Speed Memory Applications. 300-304 - King Hann Lim, Kah Phooi Seng, Li-Minn Ang, Siew Wen Chin:
Lyapunov Theory-Based Multilayered Neural Network. 305-309 - Liang Chen, Junan Lu, Chi Kong Tse:
Synchronization: An Obstacle to Identification of Network Topology. 310-314 - Heinz Koeppl:
A Local Nonlinear Model for the Approximation and Identification of a Class of Systems. 315-319 - Chuan-Ke Zhang, Yong He, Min Wu:
Improved Global Asymptotical Synchronization of Chaotic Lur'e Systems With Sampled-Data Control. 320-324 - Shengyuan Xu, Wei Xing Zheng, Yun Zou:
Passivity Analysis of Neural Networks With Time-Varying Delays. 325-329 - Daesik Park, Chester Sungchung Park, Kwyro Lee:
Simple Design of Detector in the Presence of Frequency Offset for IEEE 802.15.4 LR-WPANs. 330-334
Volume 56-II, Number 5, May 2009
- Lucien J. Breems, Peter R. Kinget, Kong-Pang Pun:
Special Issue on Circuits and Systems Solutions for Nanoscale CMOS Design Challenges. 337-338 - Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng:
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. 339-343 - John A. McNeill, Christopher L. David, Michael C. W. Coln, Rosa Croughwell:
"Split ADC" Calibration for All-Digital Correction of Time-Interleaved ADC Errors. 344-348 - Tajeshwar Singh, Trond Sæther, Trond Ytterdal:
Feedback Biasing in Nanoscale CMOS Technologies. 349-353 - Shih-An Yu, Peter R. Kinget:
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance. 354-358 - Shih-Hung Chen, Ming-Dou Ker:
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs. 359-363 - Timmy Sundström, Atila Alvandpour:
Utilizing Process Variations for Reference Generation in a Flash ADC. 364-368 - Mu-Chen Huang, Shen-Iuan Liu:
A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator. 369-373 - Armin Tajalli, Yusuf Leblebici:
Leakage Current Reduction Using Subthreshold Source-Coupled Logic. 374-378 - Yiming Li, Chih-Hong Hwang, Tien-Yeh Li:
Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit. 379-383 - Hamidreza Rezaee-Dehsorkh, Nassim Ravanshad, Reza Lotfi, Khalil Mafinezhad:
Modified Model for Settling Behavior of Operational Amplifiers in Nanoscale CMOS. 384-388 - Kadaba Lakshmikumar:
Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions. 389-393 - Jyu-Yuan Lai, Chih-Tsun Huang:
A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography. 394-398 - Tae Ho Im, Insoo Park, Jinmin Kim, Joo-Hyun Yi, Jaekwon Kim, Sungwook Yu, Yong Soo Cho:
A New Signal Detection Method for Spatially Multiplexed MIMO Systems and Its VLSI Implementation. 399-403 - Shiann-Rong Kuang, Jiun-Ping Wang, Cang-Yuan Guo:
Modified Booth Multipliers With a Regular Partial Product Array. 404-408 - Alfonso Fernández-Vázquez, Gordana Jovanovic-Dolecek:
A General Method to Design GCF Compensation Filter. 409-413 - Xingwen Liu:
Stability Analysis of Switched Positive Systems: A Switched Linear Copositive Lyapunov Function Method. 414-418 - Jaehoon Song, Juhee Han, Hyunbean Yi, Taejin Jung, Sungju Park:
Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults. 419-423
Volume 56-II, Number 6, June 2009
- Jerry C. Wu, Mona E. Zaghloul:
Robust CMOS Micromachined Inductors With Structure Supports for Gilbert Mixer Matching Circuits. 429-433 - Mark S. Oude Alink, André B. J. Kokkeler, Eric A. M. Klumperink, Kenneth C. Rovers, Gerard J. M. Smit, Bram Nauta:
Spurious-Free Dynamic Range of a Uniform Quantizer. 434-438 - Frédéric Broydé, Evelyne Clavelier:
Signal and Noise Analysis of an MIMO-SSFA. 439-443 - Marvin Onabajo, José Silva-Martínez, Félix O. Fernandez-Rodriguez, Edgar Sánchez-Sinencio:
An On-Chip Loopback Block for RF Transceiver Built-In Test. 444-448 - Jaeha Kim:
On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs. 449-453 - Saihua Lin, Dawei Huang, Simon Wong:
Pi Coil: A New Element for Bandwidth Extension. 454-458 - Francesco Centurelli, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti:
Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies. 459-463 - Guansheng Li, Yahya M. Tousi, Arjang Hassibi, Ehsan Afshari:
Delay-Line-Based Analog-to-Digital Converters. 464-468 - Bo Yuan, Zhongfeng Wang, Li Li, Minglun Gao, Jin Sha, Chuan Zhang:
Area-efficient reed-solomon decoder design for optical communications. 469-473 - Amit Golander, Shlomo Weiss, Ronny Ronen:
Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. 474-478 - Yen-Jen Chang:
A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup. 479-483 - Chris Winstead, Sheryl L. Howard:
A Probabilistic LDPC-Coded Fault Compensation Technique for Reliable Nanoscale Computing. 484-488 - Aryan Saadat Mehr:
Alias-Component Matrices of Multirate Systems. 489-493 - Yong Xiang, Sze Kui Ng:
An Approach to Nonirreducible MIMO FIR Channel Equalization. 494-498 - Zhongyang Fei, Huijun Gao, Wei Xing Zheng:
New Synchronization Stability of Complex Networks With an Interval Time-Varying Coupling Delay. 499-503 - Deyi Li, Kun Liu, Yan Sun, MingChang Han:
Emerging Clapping Synchronization From a Complex Multiagent Network With Local Information via Local Control. 504-508 - Calin Vladeanu, Safwan El Assad, Jean-Claude Carlach, Raymond Quéré:
Improved Frey Chaotic Digital Encoder for Trellis-Coded Modulation. 509-513 - Junchan Zhao, Junan Lu, Qunjiao Zhang:
Pinning a Complex Delayed Dynamical Network to a Homogenous Trajectory. 514-518 - Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu:
Comments on "A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology". 519 - Mohammad Saleh Tavazoei:
Comments on "Stability Analysis of a Class of Nonlinear Fractional-Order Systems". 519-520
Volume 56-II, Number 7, July 2009
- Chao-Ching Hung, Shen-Iuan Liu:
A Leakage-Compensated PLL in 65-nm CMOS Technology. 525-529 - Martin Anderson, Lars Sundström:
DT Modeling of Clock Phase-Noise Effects in LP CT DeltaSigma ADCs With RZ Feedback. 530-534 - Mohammad A. Al-Shyoukh, Hoi Lee:
A Compact Ramp-Based Soft-Start Circuit for Voltage Regulators. 535-539 - Lei Zhang, Zhiping Yu, Xiangqing He:
Design and Implementation of Ultralow Current-Mode Amplifier for Biosensor Applications. 540-544 - I-Hsin Wang, Hwei-Yu Lee, Shen-Iuan Liu:
An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter. 545-549 - Rui Yu, Yong Ping Xu:
Electromechanical-Filter-Based Bandpass Sigma-Delta Modulator. 550-554 - I-Ting Lee, Kun-Hung Tsai, Shen-Iuan Liu:
A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider. 555-559 - Yong-Joon Jeon, Young-Suk Son, Jinyong Jeon, Gyu-Hyeong Cho:
Improved Transient Current Feedforward Output Buffer for Fast and Compact Active-Matrix OLED Column Drivers. 560-564 - I. Faik Baskaya, David V. Anderson, Sung Kyu Lim:
Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing. 565-569 - Mohamed El-Nozahi, Edgar Sánchez-Sinencio, Kamran Entesari:
Power-Aware Multiband-Multistandard CMOS Receiver System-Level Budgeting. 570-574 - Alfonso Chacon-Rodriguez, Franco Martin-Pirchio, Silvana Sanudo, Pedro Julián:
A Low-Power Integrated Circuit for Interaural Time Delay Estimation Without Delay Lines. 575-579 - Shiyan Hu, Zhuo Li, Charles J. Alpert:
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment. 580-584 - Renatas Jakushokas, Eby G. Friedman:
Inductance Model of Interdigitated Power and Ground Distribution Networks. 585-589 - Thibault Hilaire:
Low-Parametric-Sensitivity Realizations With Relaxed L2-Dynamic-Range-Scaling Constraints. 590-594