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ORCIDISSCC 2009: San Francisco, CA, USA
- IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009. IEEE 2009, ISBN 978-1-4244-3458-9
Paper Sessions
Plenary Session
- René Penning de Vries, William Redman-White, Raf Roovers, Leo Warmerdam, Ted Letavic:
Leaner and greener: Adapting to a changing climate of innovation. 8-13 - Kiyoo Itoh:
Adaptive circuits for the 0.5-V nanoscale CMOS era. 14-20 - Mark Bohr:
The new era of scaling in an SoC world. 23-28 - John Cohn:
Kids today! Engineers tomorrow? 29-35
Imagers
- Vyshnavi Suntharalingam, Robert Berger, Stewart Clark, Jeffrey M. Knecht, Andrew Messier, Kevin Newcomb, Dennis Rathman, Richard Slattery, Antonio M. Soares, Charles Stevenson, Keith Warner, Douglas Young, Lin Ping Ang, Barmak Mansoorian
, David C. Shaver:
A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor. 38-39 - Lucio Carrara, Cristiano Niclass, Noémy Scheidegger, Herbert Shea, Edoardo Charbon:
A gamma, x-ray and high energy proton radiation-tolerant CIS for space applications. 40-41 - Ronald Kapusta, Hiroto Shinozaki, Eitake Ibaragi, Kevin Ni, Richard Wang, Mark T. Sayuk, Larry Singer, Katsu Nakamura:
A 4-channel 20-to300 Mpixel/s analog front-end with sampled thermal noise below kT/C for digital SLR cameras. 42-43 - Nagataka Tanaka, Junji Naruse, Akiko Mori, Ryuta Okamoto, Hirofumi Yamashita, Makoto Monoi:
A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation. 44-45 - Pierre-François Rüedi, Pascal Heim, Steve Gyger, François Kaess, Claude Arm, Ricardo Caseiro, Jean-Luc Nagel, Silvio Todeschini:
An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications. 46-47 - Ryu Shimizu, Mamoru Arimoto, Hayato Nakashima, Kaori Misawa, Kazuhiro Suzuki, Toshikazu Ohno, Yugo Nose, Keisuke Watanabe, Tatsushi Ohyama, Kuniyuki Tani:
A charge-multiplication CMOS image sensor suitable for low-light-level imaging. 50-51 - Anthony Huggett, Chris Silsby, Sergi Cami, Jeff Beck:
A dual-conversion-gain video sensor with dewarping and overlay on a single chip. 52-53
Microprocessor Technologies
- Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli:
A 45nm 8-core enterprise Xeon® processor. 56-57 - Rajesh Kumar, Glenn Hinton:
A family of 45nm IA processors. 58-59 - Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno:
A chip-stacked memory for on-chip SRAM-rich SoCs and processors. 60-61 - Andrew Allen, Jay Desai, Frank Verdico, Ferd Anderson, David Mulvihill, Dan Krueger:
Dynamic frequency-switching clock system on a quad-core Itanium® processor. 62-63 - Carlos Tokunaga, David T. Blaauw:
Secure AES engine with a local switched-capacitor current equalizer. 64-65 - Byungsub Kim, Vladimir Stojanovic:
A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS. 66-67 - Kyoungho Woo, Scott E. Meninger, Thucydides Xanthopoulos, Ethan Crain, Dongwan Ha, Donhee Ham:
Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring. 68-69 - Ravi Kuppuswamy, Shankar R. Sawant, Srikanth Balasubramanian, Pradeep Kaushik, Narayanan Natarajan, Jeffrey D. Gilbert:
Over one million TPCC with a 45nm 6-core Xeon® CPU. 70-71
High-Speed Data Converters
- Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult:
A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS. 74-75 - Erkan Alpman, Hasnain Lakdawala, L. Richard Carley, Krishnamurthy Soumyanath:
A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS. 76-77 - Robert C. Taft, Pier Andrea Francese, Maria Rosaria Tursi, Ols Hidri, Alan MacKenzie, Tobias Hoehn, Philipp Schmitz, Heinz Werker, Andrew Glenny:
A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency. 78-79 - Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang:
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. 80-81 - Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. 82-83 - Ashutosh Verma, Behzad Razavi:
A 10b 500MHz 55mW CMOS ADC. 84-85 - Siddharth Devarajan, Larry Singer, Dan Kelly, Steven Decker, Abhishek Kamath, Paul Wilkins:
A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC. 86-87
Potpourri: PLL, Optical, DSL
- Song-Yu Yang, Wei-Zen Chen:
A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS. 90-91 - Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee:
Subharmonically injection-locked PLLs for ultra-low-noise clock generation. 92-93 - Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman:
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. 94-95 - Sujiang Rong, Alan W. L. Ng, Howard C. Luong:
0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µm CMOS. 96-97 - Kyu-Hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman:
A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. 98-99 - Sushmit Goswami, Jason Silver, Tino Copani, Wenjian Chen, Hugh J. Barnaby, Bert Vermeire, Sayfe Kiaei:
A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects. 100-101 - Jisook Yun, Mikyung Seo, Boo-Young Choi, Jung-Won Han, Yunsung Eo, Sung Min Park:
A 4Gb/s current-mode optical transceiver in 0.18µm CMOS. 102-103 - Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto:
Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. 104-105 - Daisuke Watanabe, Atsushi Ono, Toshiyuki Okayasu:
CMOS optical 4-PAM VCSEL driver with modal-dispersion equalizer for 10Gb/s 500m MMF transmission. 106-107 - Giovanni Cesura, Alessandro Bosi, Francesco Rezzi, Rinaldo Castello, Jenkin Chan, SaiBun Wong, Chi Fan Yung, Ovidiu Carnu, Thomas Cho:
A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver. 108-109
Cellular and Tuner
- Rajasekhar Pullela, Shahrzad Tadjpour, Dmitriy Rozenblit, William Domino, Thomas Obkircher, Mohamed El Said, Bala Ramachandran, Tirdad Sowlati, Darioush Agahi, Wei-Hong Chen, Dean A. Badillo, Masoud Kahrizi, Jaleh Komaili, Stephane Wloczysiak, Utku Seckin, Yunyoung Choi, Hasan Akyol, Martin Vadkerti, Amir Mahjoob, Hamid Firouzkouhi, Dan Shum, Rajendra Suhanthan, Nooshin Vakilian, Tom Valencia, Christophe Dantec, Aaron Paff, Mona Ahooie:
An integrated closed-loop polar transmitter with saturation prevention and low-IF receiver for quad-band GPRS/EDGE. 112-113 - Olivier Gaborieau, Sven Mattisson, Nikolaus Klemmer, Bassem Fahs, Fabio T. Braz, Richard Gudmundsson, Thomas Mattsson, Carine Lascaux, Christophe Trichereau, Wen Suter, Eric Westesson, Andreas Nydahl:
A SAW-less multiband WEDGE receiver. 114-115 - Tirdad Sowlati, Bipul Agarwal, J. Cho, Thomas Obkircher, Mohamed El Said, John Vasa, Bala Ramachandran, Masoud Kahrizi, Elias Dagher, Wei-Hong Chen, Martin Vadkerti, Georgi Taskov, Utku Seckin, Hamid Firouzkouhi, Behzad Saeidi, Hasan Akyol, Yunyoung Choi, Amir Mahjoob, Sandeep D'Souza, Chieh-Yu Hsieh, David Guss, Dan Shum, Dean A. Badillo, Imtiyaz Ron, Doris Ching, Feng Shi, Yong He, Jaleh Komaili, Aravind Loke, Rajasekhar Pullela, Engin Pehlivanoglu, Hossein Zarei, Shahrzad Tadjpour, Darioush Agahi, Dmitriy Rozenblit, William Domino, Gregory Williams, Nader Damavandi, Stephane Wloczysiak, Suhanthan Rajendra, Aaron Paff, Tom Valencia:
Single-chip multiband WCDMA/HSDPA/HSUPA/EGPRS transceiver with diversity receiver and 3G DigRF interface without SAW filters in transmitter / 3G receiver paths. 116-117 - Aristotele Hadjichristos, Marco Cassia, Hong Sun Kim, C. H. Park, Kevin Wang, W. Zhuo, Bahman Ahrari, Roger Brockenbrough, J. Chen, Conor Donovan, R. Jonnalagedda, J. Kim, Jin-Su Ko, Hee Choul Lee, Sang Oh Lee, Emilia Lei, T. Nguyen, T. Pan, S. Sridhara, W. Su, H. Yan, J. Yang, Cormac Conroy, Charles J. Persico, Kamal Sahota, B. Kim:
Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPS. 118-119 - Xin He, Jan van Sinderen:
A 45nm low-power SAW-less WCDMA transmit modulator using direct quadrature voltage modulation. 120-121 - Francesco Gatta, Ray Gomez, Young Shin, Takayuki Hayashi, Hanli Zou, James Y. C. Chang, Leonard Dauphinee, Jianhong Xiao, Dave S.-H. Chang, Tai-Hong Chih, Massimo Brandolini, Dongsoo Koh, Bryan Juo-Jung Hung, Tao Wu, Mattia Introini, Giuseppe Cusmai, Loke Tan, Bruce Currivan, Lin He, Peter Cangiane, Pieter Vorenkamp:
An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0. 122-123 - Yi-Ti Huang, C. M. Yang, S. C. Huang, H. L. Pan, T. C. Hung:
A 1.2V 67mW 4mm2 mobile ISDB-T tuner in 0.13µm CMOS. 124-125
DRAM
- Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim:
1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. 128-129 - Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim:
8Gb 3D DDR3 DRAM using through-silicon-via technology. 130-131 - Bong Hwa Jeong, Jongwon Lee, Yin Jae Lee, Tae Jin Kang, Joo Hyeon Lee, Duck Hwa Hong, Jae Hoon Kim, Eun Ryeong Lee, Min Chang Kim, Kyung Ha Lee, Sang Il Park, Jong Ho Son, Sang Kwon Lee, Seong Nyuh Yoo, Sung Mook Kim, Tae Woo Kwon, Jin-Hong Ahn, Yong Tak Kim:
A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application. 132-133 - Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein:
75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. 134-135 - Hamid Partovi, Karthik Gopalakrishnan, Luca Ravezzi, Russell Homer, Otto Schumacher, Reinhold Unterricker, Werner Kederer:
Single-ended transceiver design techniques for 5.33Gb/s graphics applications. 136-137 - Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim:
A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. 138-139 - Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung:
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. 140-141 - Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh:
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. 142-143
Multimedia Processors
- Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply. 146-147 - Yuya Hanai, Yuichi Hori, Jun Nishimura, Tadahiro Kuroda:
A versatile recognition processor employing Haar-like feature and cascaded classifier. 148-149 - Joo-Young Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, Kwanho Kim, Sejong Oh, Jeong-Ho Woo, Donghyun Kim, Hoi-Jun Yoo:
A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine. 150-151 - Chi-Cheng Ju, Tsu-Ming Liu, Chih-Chieh Yang, Shih-Hung Lin, Kuo-Pin Lan, Chien-Hua Wu, Ting-Hsun Wei, Chi-Chin Lien, Jiun-Yuan Wu, Chih-Hao Hsiao, Te-Wei Chen, Yeh-Lin Chu, Guan-Yi Lin, Yung-Chang Chang, Kung-Sheng Lin, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Chien-Hung Lin, Yung-Teng Lin, Shang-Ming Lee, Ya-Ching Yang, Yu-Lun Cheng, Chen-Chia Lee, Ming-Shiang Lai, Wen-Hua Wu, Ted Hu, Chao-Wei Tseng, Chen-Yu Hsiao, Wei-Liang Lee, Bo-Jiun Chen, Pao-Cheng Chiu, Shang-Ping Chen, Kun-Hsien Li, Kuan-Hua Chao, Chien-Ming Chen, Chuan-Cheng Hsiao, Jeffrey Ju, Wei-Hung Huang, Chi-Hui Wang, Hung-Sung Li, Evan Su, Joe Chen:
A multi-format Blu-ray player SoC in 90nm CMOS. 152-153 - Li-Fu Ding, Wei-Yin Chen, Pei-Kuei Tsung, Tzu-Der Chuang, Hsu-Kuang Chiu, Yu-Han Chen, Pai-Heng Hsiao, Shao-Yi Chien, Tung-Chien Chen, Ping-Chih Lin, Chia-Yu Chang, Liang-Gee Chen:
A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications. 154-155 - Motoyasu Shirasaki, Yusaku Miyazaki, Masahiro Hoshaku, Hiroo Yamamoto, Sachio Ogawa, Takuya Arimura, Hiroshi Hirai, Yasuo Iizuka, Tsutomu Sekibe, Yoichi Nishida, Toshiyuki Ishioka, Junji Michiyama:
A 45nm single-chip application-and-baseband processor using an intermittent operation technique. 156-157 - Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342mW mobile application processor with full-HD multi-standard video codec. 158-159
Data Converter Techniques
- Andrea Panigada, Ian Galton:
A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction. 162-163 - Imran Ahmed, Jan Mulder, David A. Johns:
A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps. 164-165 - Lane Brooks, Hae-Seung Lee:
A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB. 166-167 - Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn:
A 9b 14µW 0.06mm2 PPM ADC in 90nm digital CMOS. 168-169 - Min C. Park, Michael H. Perrott:
A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer. 170-171 - Sheng-Jui Huang, Yung-Yu Lin:
A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with -97.7dBc THD and 80dB DR using low-latency DEM. 172-173 - Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz:
A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element. 174-175 - Lynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, Geert Van der Plas:
A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS. 176-177
Multi-Gb/s Serial Links and Building Blocks
- Lidong Chen, Xuguang Zhang, Fulvio Spagna:
A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS. 180-181 - Yong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman:
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. 182-183 - Seon-Kyoo Lee, Young-Sang Kim, Hyunsoo Ha, Young Hun Seo, Hong-June Park, Jae-Yoon Sim:
A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate. 184-185 - Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito:
10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1st-order ΔΣ modulator. 186-187 - Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone:
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. 188-189 - Yan-Bin Luo, Ping Chen, Qui-Ting Chen, Chih-Yong Wang, Chan-Hao Chang, Szu-Jui Fu, Chien-Ming Chen, Hung-Sung Li:
A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer. 190-191 - Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama:
A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. 192-193
TD: Trends in Wireless Communications
- Pierre Vincent, Marie Claire Cyrille, Bernard Viala, Bertrand Delaet, Jean-Philippe Michel, Patrick Villard, Jérôme Prouvée, Dimitri Houssameddine, Ursula Ebels, Jordan A. Katine, Daniele Mauri, Sylvia Florez, Ozhan Ozatay, Liesl Folks, Bruce D. Terris, Franck Badets:
A GHz spintronic-based RF oscillator. 196-197 - Majid Baghaei Nejad, David S. Mendoza, Zhuo Zou, Soheil Radiom, Georges G. E. Gielen, Li-Rong Zheng, Hannu Tenhunen:
A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOS. 198-199 - Denis C. Daly, Patrick P. Mercier, Manish Bhardwaj, Alice L. Stone, Joel Voldman, Richard B. Levine, John G. Hildebrand, Anantha P. Chandrakasan:
A pulsed UWB receiver SoC for insect motion control. 200-201 - Swaminathan Sankaran, Chuying Mao, Eunyoung Seok, Dongha Shim, Changhua Cao, Ruonan Han, Daniel J. Arenas, David B. Tanner, Stephen Hill, Chih-Ming Hung, Kenneth K. O:
Towards terahertz operation of CMOS. 202-203 - Alberto Fazzi, Sotir Ouzounov, John van den Homberg:
A 2.75mW wideband correlation-based transceiver for body-coupled communication. 204-205 - Kris Myny, Monique J. Beenhakkers, Nick A. J. M. van Aerle, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans:
A 128b organic RFID transponder chip, including Manchester encoding and ALOHA anti-collision protocol, operating with a data rate of 1529b/s. 206-207 - Robert Blache, Jürgen Krumm, Walter Fix:
Organic CMOS circuits for RFID applications. 208-209 - David Ruffieux, Aurélie Pezous, Anne-Claire Pliska, François Krummenacher:
Silicon-resonator-based, 3µA real-time clock with ±5ppm frequency accuracy. 210-211 - Shailesh Rai, Jeremy Holleman, Jagdish Nayayan Pandey, Fan Zhang, Brian P. Otis:
A 500µW neural tag with 2µVrms AFE and frequency-multiplying MICS/ISM FSK transmitter. 212-213
RF Building Blocks
- Daniele Mastantuono, Danilo Manstretta:
A low-noise active balun with IM2 cancellation for multiband portable DVB-H receivers. 216-217 - Sanghyun Woo, Woonyun Kim, Chang-Ho Lee, Kyutae Lim, Joy Laskar:
A 3.6mW differential common-gate CMOS LNA with positive-negative feedback. 218-219 - Yu-Jiu Wang, Ali Hajimiri:
A compact low-noise weighted distributed amplifier in CMOS. 220-221 - Michiel C. M. Soer, Eric A. M. Klumperink, Zhiyu Ru, Frank E. van Vliet, Bram Nauta:
A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF. 222-223 - Jun Deguchi, Daisuke Miyashita, Mototsugu Hamada:
A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner. 224-225 - Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas:
A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS. 226-227 - Emanuele Lopelli, Johan van der Tang, Kathleen Philips, Arthur H. M. van Roermund, Bert Gyselinckx:
A 0.75V 325µW 40dB-SFDR frequency-hopping synthesizer for wireless sensor networks in 90nm CMOS. 228-229 - Zhiyu Ru, Eric A. M. Klumperink, Gerard Wienk, Bram Nauta:
A software-defined radio receiver architecture robust to out-of-band interference. 230-231 - Niels A. Moseley, Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta:
A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation. 232-233
Flash Memory
- Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama:
A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS. 236-237 - Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. 238-239 - Seung-Ho Chang, Sok-Kyu Lee, Seong-Je Park, Min-Joong Jung, Jung-Chul Han, In-Soo Wang, Kyu-Hee Lim, Jung-Hwan Lee, Ji-Hwan Kim, Won-Kyung Kang, Tai-Kyu Kang, Hee-Su Byun, Yujong Noh, Lee-Hyun Kwon, Bon-Kwang Koo, Myung Cho, Joong-Seob Yang, Yo-Hwan Koh:
A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughput. 240-241 - Takuya Futatsuyama, Norihiro Fujita, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Teruhiko Kamei, Hiroaki Nasu, Makoto Iwai, Koji Kato, Yasuyuki Fukuda, Naoaki Kanagawa, Naofumi Abiko, Masahide Matsumoto, Toshihiko Himeno, Toshifumi Hashimoto, Yi-Ching Liu, Hardwell Chibvongodze, Takamitsu Hori, Manabu Sakai, Hong Ding, Yoshiharu Takeuchi, Hitoshi Shiga, Norifumi Kajimura, Yasuyuki Kajitani, Kiyofumi Sakurai, Kosuke Yanagidaira, Toshihiro Suzuki, Yuko Namiki, Tomofumi Fujimura, Man Mui, Hao Nguyen, Seungpil Lee, Alex Mak, Jeffery Lutze, Tooru Maruyama, Toshiharu Watanabe, Takahiko Hara, Shigeo Ohshima:
A 113mm2 32Gb 3b/cell NAND flash memory. 242-243 - Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. 244-245 - Cuong Trinh, Noboru Shibata, Takeshi Nakano, Mikio Ogawa, Jumpei Sato, Yoshikazu Takeyama, Katsuaki Isobe, Binh Le, Farookh Moogat, Nima Mokhlesi, Kenji Kozakai, Patrick Hong, Teruhiko Kamei, Kiyoaki Iwasa, J. Nakai, Takahiro Shimizu, Mitsuaki Honma, Shintaro Sakai, Toshimasa Kawaai, Satoru Hoshi, Jonghak Yuh, Cynthia Hsu, Taiyuan Tseng, Jason Li, Jayson Hu, M. Liu, Shahzad Khalid, J. Chen, Mitsuyuki Watanabe, Hung-Szu Lin, Junhui Yang, K. McKay, Khanh Nguyen, Tuan Pham, Y. Matsuda, K. Nakamura, Kazunori Kanebako, Susumu Yoshikawa, W. Igarashi, Atsushi Inoue, T. Takahashi, Yukio Komatsu, C. Suzuki, Kousuke Kanazawa, Masaaki Higashitani, Seungpil Lee, T. Murai, K. Nguyen, James Lan, Sharon Huynh, Mark Murin, Mark Shlick, Menahem Lasser, Raul Cernea, Mehrdad Mofidi, K. Schuegraf, Khandker Quader:
A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS. 246-247
Digital Wireless and Reconfigurability
- Marian Verhelst, Nick Van Helleputte, Georges G. E. Gielen, Wim Dehaene:
A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging. 250-251 - Patrick P. Mercier, Manish Bhardwaj, Denis C. Daly, Anantha P. Chandrakasan:
A 0.55V 16Mb/s 1.6mW non-coherent IR-UWB digital baseband with ±1ns synchronization accuracy. 252-253 - J.-M. Wei, C.-N. Chen, K.-T. Chen, C.-F. Kuo, B.-H. Ong, C.-H. Lu, C.-C. Liu, H.-C. Chiou, H.-C. Yeh, J.-H. Shieh, K.-S. Huang, K.-I. Li, M.-J. Wu, M.-H. Li, S.-H. Chou, Soong Lin Chew, W.-L. Lien, W.-G. Yau, W.-Z. Ge, W.-C. Lai, W.-H. Ting, Y.-J. Tsai, Y.-C. Yen, Y.-C. Yeh:
A 110nm RFCMOS GPS SoC with 34mW -165dBm tracking sensitivity. 254-255 - Mahdi Shabany, P. Glenn Gulak:
A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO detector. 256-257