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"A 0.7-2-GHz self-calibrated multiphase delay-locked loop."

Hsiang-Hui Chang et al. (2006)

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DOI: 10.1109/JSSC.2006.874036

access: closed

type: Journal Article

metadata version: 2021-10-15

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  - journals/jssc/ChangCKL06
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  - https://dblp.org/rec/journals/jssc/ChangCKL06
Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu:
A 0.7-2-GHz self-calibrated multiphase delay-locked loop. IEEE J. Solid State Circuits 41(5): 1051-1061 (2006)

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