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ORCIDIEEE Journal of Solid-State Circuits, Volume 34
Volume 34, Number 1, January 1999
- Jaejin Park, Eurho Joe, Myung-Jun Choe, Bang-Sup Song:
A 5-MHz IF digital FM demodulator. 3-11 - Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino:
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. 12-17 - Kenichi Ohhata, Toru Masuda, Kazuo Imai, Ryoji Takeyari, Katsuyoshi Washio:
A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links. 18-24 - Mohammad Madihian, Tomislav Drenski, Laurent Desclos, Hiroshi Yoshida, Hiroshi Hirabayashi, Tohru Yamazaki:
A 5-GHz-band multifunctional BiCMOS transceiver chip for GMSK modulation wireless systems. 25-32 - Akira Ohta, Norio Higashisaka, Tetsuya Heima, Takayuki Hisaka, Hirofumi Nakano, Ryuji Ohmura, Tadashi Takagi, Noriyuki Tanino:
A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure. 33-41 - Jean Michel Daga, Daniel Auvergne:
A comprehensive delay macro modeling for submicrometer CMOS logics. 42-55 - Wei Hwang, Rajiv V. Joshi, Walter H. Henkels:
A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file. 56-67 - Yuh-Kuang Tseng, Chung-Yu Wu:
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications. 68-79 - Mohamed Nekili, Yvon Savaria, Guy Bois:
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. 80-84 - Nick Lindert, Toshihiro Sugii, Stephen Tang, Chenming Hu:
Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages. 85-89 - Vincent Wing-Yun Sit, Chiu-Sing Choy, Cheong-Fat Chan:
A four-phase handshaking asynchronous static RAM design for self-timed systems. 90-96 - Joao Navarro Soares, Wilhelmus A. M. Van Noije:
A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC). 97-102 - Steve H. Jen, Bing J. Sheu, Yoondong Park:
A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's. 103-106 - Barbaros Sekerkiran:
A compact rail-to-rail output stage for CMOS operational amplifiers. 107-110 - K. R. Lakshmikumar, J. Anidjar:
A low-voltage line driver for digital signaling interface. 111-115 - Pang-Cheng Yu, Jiin-Chuan Wu:
A class-B output buffer for flat-panel-display column driver. 116-119 - Joaquín Portilla
, Héctor García, Eduardo Artal:
High power-added efficiency MMIC amplifier for 2.4 GHz wireless communications. 120-123 - Robert H. Caverly:
Linear and nonlinear characteristics of the silicon CMOS monolithic 50-Ω microwave and RF control element. 124-126 - Loke Kun Tan, Jeffrey S. Putnam, Fang Lu, Lionel J. D'Luna, Dean W. Mueller, Kenneth R. Kindsfater, Kelly B. Cameron, Robindra B. Joshi, Robert A. Hawley, Henry Samueli:
Correction to "A 70-Mb/s Variable-Rate 1024-QAM Cable Receiver IC with Integrated 10-b ADC and FEC Decoder". 127 - Clemens M. Hammerschmied, Qiuting Huang:
Addition to "Design and Implementation of an Untrimmed MOSFET-Only 10-bit A/D Converter with -79-dB THD". 127
Volume 34, Number 3, March 1999
- Behzad Razavi:
CMOS technology characterization for analog and RF design. 268-276 - Tajinder Manku:
Microwave CMOS-device physics and design. 277-285 - Joo Leong (Julian) Tham, Mihai A. Margarit, Bernd Prégardier, Christopher D. Hull, Rahul Magoon, Frank Carr:
A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digital wireless communication. 286-291 - Qiuting Huang, Paolo Orsatti, Francesco Piazza:
GSM transceiver front-end circuits in 0.25-μm CMOS. 292-303 - Ravindranath Naiknaware, Terri S. Fiez:
Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations. 304-303 - Ravindranath Naiknaware, Terri S. Fiez:
Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations. 304-317 - Benoit Dufort, Gordon W. Roberts:
On-chip analog signal generation for mixed-signal built-in self-test. 318-330 - Tao Shui, Richard Schreier, Forrest Hudson:
Mismatch shaping for a current-mode multibit delta-sigma DAC. 331-338 - Hiok-Tiaq Ng, Ramsin M. Ziazadeh, David J. Allstot:
A multistage amplifier technique with embedded frequency compensation. 339-347 - David X. D. Yang, Boyd Fowler, Abbas El Gama:
A Nyquist-rate pixel-level ADC for CMOS image sensors. 348-356 - Hiroshi Iwai:
CMOS technology-year 2010 and beyond. 357-366 - Jone F. Chen, Jiang Tao, Peng Fang, Chenming Hu:
Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates. 367-371 - Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, Hisamitsu Suzuki:
A direct-skew-detect synchronous mirror delay for application-specific integrated circuits. 372-379 - Bevan M. Baas:
A low-power, high-performance, 1024-point FFT processor. 380-387 - Wolfgang Wilhelm:
A new scalable VLSI architecture for Reed-Solomon decoders. 388-396 - Byoung-Woon Kim, Jin-Hyuk Yang, Chan-Soo Hwang, Young-Su Kwon, Keun-Moo Lee, In-Hyoung Kim, Yong-Hoon Lee, Chong-Min Kyung:
MDSP-II: a 16-bit DSP with mobile communication accelerator. 397-404 - Hema Kapadia, Luca Benini, Giovanni De Micheli:
Reducing switching activity on datapath buses with control-signal gating. 405-414 - Christian Menolfi, Qiuting Huang:
A fully integrated, untrimmed CMOS instrumentation amplifier with submicrovolt offset. 415-420
Volume 34, Number 4, April 1999
- Loai Louis, John Abcarius, Gordon W. Roberts:
An eighth-order bandpass ΔΣ modulator for A/D conversion in digital radio. 423-431 - Sunny S. W. Chan, Philip C. H. Chan:
A resistance-variation-tolerant constant-power heating circuit for integrated sensor applications. 432-439 - Clark T.-C. Nguyen, Roger T. Howe:
An integrated CMOS micromechanical resonator high-Q oscillator. 440-455 - Mark Lemkin, Bernhard E. Boser:
A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics. 456-468 - Jeong-Woo Lee, Dong-Jin Min, Jiyoun Kim, Wonchan Kim:
A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique. 469-475 - Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka:
New three-dimensional memory array architecture for future ultrahigh-density DRAM. 476-483 - Daeyun Shim, Dong-Yun Lee, Sanghun Jung, Chang-Hyun Kim, Wonchan Kim:
An analog synchronous mirror delay for high-speed DRAM application. 484-493 - Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada:
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. 494-501 - Kazuya Yamamoto, Takao Moriwaki, Takayuki Fujii, Jun Otsuji, Miyo Miyashita, Yukio Miyazaki, Kazuo Nishitani:
A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver for wireless applications. 502-512 - David W. Boerstler:
A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz. 513-519 - Gu-Yeon Wei, Mark Horowitz:
A fully digital, energy-efficient, adaptive power-supply regulator. 520-528 - Jae-Yoon Sim, Young-Soo Sohn, Seung-Chan Heo, Hong-June Park, Soo-In Cho:
A 1-Gb/s bidirectional I/O buffer using the current-mode scheme. 529-535 - Vladimir Stojanovic, Vojin G. Oklobdzija:
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. 536-548 - M. Omair Ahmad, Shenghong Wang:
A design and implementation of fully programmable switched-current IIR filters. 549-553 - Shen-Iuan Liu, Jiunn-Hwa Lee, Hen-Wai Tsao:
Low-power clock-deskew buffer for high-speed digital circuits. 554-558 - Kamel Ayadi:
High-speed, highly sensitive OEIC using clocked vertical BJT's photoDarlington in CMOS technology. 559-564 - Feng Lin, Jason Miller, Aaron Schoenfeld, Manny Ma, R. Jacob Baker:
A register-controlled symmetrical DLL for double-data-rate DRAM. 565-568
Volume 34, Number 5, May 1999
- William Bidermann, Masao Taguchi:
Guest Editorial. 571-572 - Behzad Razavi:
A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications. 573-579 - Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee:
A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter. 580-585 - Chan-Hong Park, Beomsup Kim:
A low-noise, 900-MHz VCO in 0.6-μm CMOS. 586-591 - Michael Q. Le, Paul J. Hurst, Kenneth C. Dyer:
An analog DFE for disk drives using a mixed-signal integrator. 592-598 - Andrew M. Abo, Paul R. Gray:
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. 599-606 - Katayoun Falakshahi, Chih-Kong Ken Yang, Bruce A. Wooley:
A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation. 607-615 - Osamu Takahashi, Naoaki Aoki, Joel Silberman, Sang H. Dhong:
A 1-GHz logic circuit family with sense amplifiers. 616-622 - Krishnamurthy Soumyanath, Shekhar Borkar, Chunyan Zhou, Bradley A. Bloechel:
Accurate on-chip interconnect evaluation: a time-domain technique. 623-631 - Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz:
A portable digital DLL for high-speed CMOS interface circuits. 632-644 - Changhyun Kim, Kye-Hyun Kyung, W.-P. Jeong, J.-S. Kim, Byung-Sik Moon, Joon-Wan Chai, S.-M. Yim, Jung-Hwan Choi, K.-H. Han, C.-J. Park, Hong-Sun Hwang, H. Choi, Sung-Burn Cho, Clemenz L. Portmann, Soo-In Cho:
A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. 645-652 - Takashi Sato, Yoji Nishio, Toshio Sugano, Yoshinobu Nakagome:
A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. 653-660 - Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada:
A 5.3-GB/s embedded SDRAM core with slight-boost scheme. 661-669 - Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, Koji Sakui:
A CMOS bandgap reference circuit with sub-1-V operation. 670-674 - Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui:
A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories. 675-684 - Hiroaki Ikeda, Hidemori Inukai:
High-speed DRAM architecture development. 685-692 - Thucydides Xanthopoulos, Anantha P. Chandrakasan:
A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity. 693-703 - Tarek Lulé, Bernd Schneider, Markus Böhm:
Design and fabrication of a high-dynamic-range image sensor in TFA technology. 704-711 - Fabian Klass, Chaim Amir, Ashutosh Das, Kathirgamar Aingaran, Cindy Truong, Richard Wang, Anup Mehta, Raymond A. Heald, Gin Yee:
A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. 712-716 - Ali Hajimiri, Thomas H. Lee:
Design issues in CMOS differential LC oscillators. 717-724 - Caesar S. Wong:
A 3-V GSM baseband transmitter. 725-730
Volume 34, Number 6, June 1999
- Hirokazu Yoshizawa, Yunteng Huang, Paul F. Ferguson Jr., Gabor C. Temes:
MOSFET-only switched-capacitor circuits in digital CMOS technology. 734-747 - Fernando Medeiro, Belén Pérez-Verdú, Ángel Rodríguez-Vázquez:
A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology. 748-760 - Mihai A. Margarit, Joo Leong Tham, Robert G. Meyer, M. Jamal Deen:
A low-noise, low-power VCO with automatic amplitude control for wireless applications. 761-771 - Manolis Terrovitis, Robert G. Meyer:
Noise in current-commutating CMOS mixers. 772-783 - Wei-Zen Chen, Jieh-Tsorng Wu:
A 2-V, 1.8-GHz BJT phase-locked loop. 784-789 - Ali Hajimiri, Sotirios Limotyrakis, Thomas H. Lee:
Jitter and phase noise in ring oscillators. 790-804 - Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino:
A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs. 805-812 - Hamid R. Rategh, Thomas H. Lee:
Superharmonic injection-locked frequency dividers. 813-821 - Akira Nakada, Tadashi Shibata, Masahiro Konda, Tatsuo Morimoto, Tadahiro Ohmi:
A fully parallel vector-quantization processor for real-time motion-picture compression. 822-830 - Jeffrey C. Gealow, Charles G. Sodini:
A pixel-parallel image processor using logic pitch-matched to dynamic memory. 831-839 - Kees van Berkel, Charles E. Molnar:
Beware the three-way arbiter. 840-848 - Charles Dike, Edward Burton:
Miller and noise effects in a synchronizing flip-flop. 849-855 - Dong-Sun Min, Dietrich W. Langer:
Multiple twisted dataline techniques for multigigabit DRAMs. 856-865 - Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe:
A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers. 866-877 - P. J. Sullivan, B. A. Xavier, Walter H. Ku:
Doubly balanced dual-gate CMOS mixer. 878-881 - Asad A. Abidi, John C. Leete:
De-embedding the noise figure of differential amplifiers. 882-885 - R. Schmid, Thomas F. Meister, Mirjana Rest, Hans-Martin Rein:
SiGe driver circuit with high output amplitude operating up to 23 Gb/s. 886-891 - Andrea Boni, Carlo Morandi, Silvia Padoan:
A 2.5-V BiCMOS comparator with current-mode interpolation. 892-897 - Joonho Lim, Dong-Gyu Kim, Soo-Ik Chae:
A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems. 898-903 - Joonbae Park, Jeongho Lee, Wonchan Kim:
Current sensing differential logic: a CMOS logic for high reliability and flexibility. 904-908
Volume 34, Number 7, July 1999
- Iuri Mehr, Declan Dalton:
A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications. 912-920 - Dan B. Kasha, Wai L. Lee, Axel Thomsen:
A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing. 921-926 - Yves Geerts, Augusto Manuel Marques, Michel S. J. Steyaert, Willy Sansen:
A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications. 927-936 - Christopher F. Edwards, William Redman-White, Mark Bracey, Bernard M. Tenbroek, Michael S. L. Lee, Michael J. Uren:
A multibit ΣΔ modulator in floating-body SOS/SOI CMOS for extreme radiation environments. 937-948 - Anne-Johan Annema:
Low-power bandgap references featuring DTMOSTs. 949-955 - John van den Homberg:
A universal 0.03-mm2 one-pin crystal oscillator in CMOS. 956-961 - King-Chun Tsai, Paul R. Gray:
A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications. 962-970 - Mark Ingels, Michel S. J. Steyaert:
A 1-Gb/s, 0.7-μm CM+ OS optical receiver with full rail-to-rail output swing. 971-977 - Stefan Jung, Roland Thewes, Thomas Scheiter, Karl F. Goser, Werner Weber:
A low-power and high-performance CMOS fingerprint sensing and encoding architecture. 978-984 - Ronan A. R. van der Zee, Ed A. J. M. van Tuijl:
A power-efficient audio amplifier combining switching and linear techniques. 985-991 - Atsushi Mohri, Akira Yamada, Y. Yoshida, Hisakazu Sato, Hidehiro Takata, K. Nakakimura, M. Hashizume, Y. Shimotsuma, K. Tsuchihashi:
A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor. 992-1000 - L. Kiss, K. Adriaensen, C. Gendarme, E. Hanssens, M. Huysmans, F. van Beylen, Hugo van de Weghe:
SACHEM, a versatile DMT-based modem transceiver for ADSL. 1001-1009 - Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina:
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. 1010-1021 - Sander L. J. Gierkink, Eric A. M. Klumperink, Arnoud P. van der Wel, Gian Hoogzaad, Ed A. J. M. van Tuijl, Bram Nauta:
Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators. 1022-1025 - John Clouser, Mark Matson, R. Badeau, R. Dupcak, Sridhar Samudrala, Randy L. Allmon, N. Fairbanks:
A 600-MHz superscalar floating-point processor. 1026-1029
Volume 34, Number 8, August 1999
- Avanindra Madisetti, Alan Y. Kwentus, Alan N. Willson Jr.:
A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range. 1034-1043 - Joseph N. Babanezhad:
A 100-MHz, 50-Ω, -45-dB distortion, 3.3-V CMOS line driver for Ethernet and fast Ethernet networking applications. 1044-1050 - Akira Nagayama, Masatoyo Nishibe, Takayuki Inaoka, Nobuhiro Mineshima:
Low-insertion-loss DP3T MMIC switch for dual-band cellular phones. 1051-1055 - K. Nagaraj, F. Chen, T. R. Viswanathan:
Efficient 6-bit A/D converter using a 1-bit folding front end. 1056-1062 - Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee:
An all-digital phase-locked loop (ADPLL)-based clock recovery circuit. 1063-1073 - Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama:
Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS. 1074-1083 - Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura:
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. 1084-1090 - Toru Tanzawa, Shigeru Atsumi:
Optimization of word-line booster circuits for low-voltage flash memories. 1091-1098 - Aaron Partridge, J. Kurth Reynolds, John D. Grade, Bart J. Kane, Nadim I. Maluf, Gregory T. A. Kovacs, Thomas W. Kenny:
An integrated controller for tunnel sensors. 1099-1107 - Wei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel:
Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability. 1108-1117 - Masoud Zargari, Justin Leung, S. Simon Wong, Bruce A. Wooley:
A BiCMOS active substrate probe-card technology for digital testing. 1118-1135 - Michael Schröter, Hans-Martin Rein, Winfried Rabe, Reinhard Reimann, Hans-Joachim Wassener, Andreas Koldehoff:
Physics- and process-based bipolar transistor modeling for integrated circuit design. 1136-1149 - Saska Lindfors, Jarkko Jussila, Kari Halonen, Lauri Siren:
A 3-V continuous-time filter with on-chip tuning for IS-95. 1150-1154 - Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Akira Yasuda, Ryuichi Fujimoto, Tadashi Arai, Hideyuki Kokatsu:
A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC. 1155-1159 - Simona Brigati, Fabrizio Francesconi, Guido Grassi, D. Lissoni, A. Nobile, Piero Malcovati, Franco Maloberti, Matteo Poletti:
An 0.8-μm CMOS mixed analog-digital integrated audiometric system. 1160-1166 - Feng-Tso Chien, Yi-Jen Chan:
Bandwidth enhancement of transimpedance amplifier by a capacitive-peaking design. 1167-1170 - Dong-Ho Shin, Young-Min Lee, Kyu-Hyoun Kim, Kwyro Lee:
Low-power dynamic termination scheme using NMOS diode clamping. 1171-1175 - Jianjun Zhou, David J. Allstot:
Addition to "Monolithic transformers and their application in a differential CMOS RF low-noise amplifier". 1176
Volume 34, Number 9, September 1999
- Isao Takenaka, Kouji Ishikura, Hidemasa Takahashi, Kazunori Asano, Junko Morikawa, K. Satou, K. Kishi, Kouichi Hasegawa, K. Tokunaga, Fumiaki Emori, Masaaki Kuzuhara:
L/S-band 140-W push-pull power AlGaAs/GaAs HFET's for digital cellular base stations. 1181-1187 - Kevin W. Kobayashi, John C. Cowles, Liem T. Tran, Augusto Gutierrez-Aitken, Matt Nishimoto, Jeffrey H. Elliott, Thomas R. Block, Aaron K. Oki, Dwight C. Streit:
A 44-GHz-high IP3 InP HBT MMIC amplifier for low DC power millimeter-wave receiver applications. 1188-1195 - Dino Mensa, Rajasekhar Pullela, Q. Lee, J. Guthrie, Suzanne C. Martin, R. P. Smith, S. Jaganathan, Thomas Mathew, Bipul Agarwal, Stephen I. Long, Mark J. W. Rodwell:
48-GHz digital ICs and 85-GHz baseband amplifiers using transferred-substrate HBT's. 1196-1203 - Jesús A. del Alamo, Mark H. Somerville:
Breakdown in millimeter-wave power InP HEMTs: a comparison with GaAs PHEMT's. 1204-1211 - M. Yu, M. Matloubian, P. Petre, L. R. Hamilton, R. Bowen, M. Lui, H.-C. Sun, C. M. Ngo, P. Janke, D. W. Baker, R. S. Robertson:
W-band InP HEMT MMICs using finite-ground coplanar waveguide (FGCPW) design. 1212-1218 - Carl W. Pobanz, M. Matloubian, M. Lui, H.-C. Sun, Michael Case, C. M. Ngo, P. Janke, Todd Gaier, Lorene Samoska:
A high-gain monolithic D-band InP HEMT amplifier. 1219-1224 - Kevin W. Kobayashi, Aaron K. Oki, Liem T. Tran, John C. Cowles, Augusto Gutierrez-Aitken, Frank Yamada, Thomas R. Block, Dwight C. Streit:
A 108-GHz InP-HBT monolithic push-push VCO with low phase noise and wide tuning bandwidth. 1225-1232 - David E. Meharry, Jay E. Sanctuary, Bogdan A. Golja:
Broad bandwidth transformer coupled differential amplifiers for high dynamic range. 1233-1238 - Thomas J. Jenkins, Lois T. Kehias, Primit Parikh, James Ibbetson, Umesh K. Mishra, Daniel Docter, Minh Le, Joe Pusl, Duncan Widman:
Ultrahigh efficiency obtained with GaAs-on-insulator MESFET technology. 1239-1245 - Yutaka Miyamoto, Mikio Yoneyama, Taiichi Otsuji, Kazushige Yonenaga, Naofumi Shimizu:
40-Gbit/s TDM transmission technologies based on ultra-high-speed ICs. 1246-1253 - Albert G. Baca, Edwin J. Heller, Vincent M. Hietala, Stephen A. Casalnuovo, Greg C. Frye-Mason, John F. Klem, T. J. Drummond:
Development of a GaAs monolithic surface acoustic wave integrated circuit. 1254-1258 - Riad Kanan, Michel J. Declercq:
PCFL3: a low-power, high-speed, single-ended logic family. 1259-1269 - Steven H. Voldman:
The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling. 1272-1282 - Christelle Delage, Nicolas Nolhier, Marise Bafleur, Jean-Marie Dorkel, Jo Hamid, Philippe Givelin, Jacques Lin-Kwang:
The mirrored lateral SCR (MILSCR) as an ESD protection structure: design and optimization using 2-D device simulation. 1283-1289 - Kenichi Ohhata, Toru Masuda, Eiji Ohue, Katsuyoshi Washio:
Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamic range implemented in SiGe HBT. 1290-1297 - Kenneth S. Kundert:
Introduction to RF simulation and its application. 1298-1319 - Martin Wurzer, Josef Böck, Herbert Knapp, Wolfgang Zirwas, Fritz Schumann, Alfred Felder:
A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz fT silicon bipolar technology. 1320-1324 - Muneo Fukaishi, Satoshi Nakamura, Akio Tajima, Yasushi Kinoshita, Yoshihiko Suemura, Hisamitsu Suzuki, Toshiro Itani, Hidenobu Miyamoto, Naoya Henmi, Tohru Yamazaki, Michio Yotsuyanagi:
A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications. 1325-1330 - Leo C. N. de Vreede, Henk C. de Graaff, Joost A. Willemen, Wibo D. van Noort, Rik Jos, Lawrence E. Larson, Jan W. Slotboom, Joseph L. Tauritz:
Bipolar transistor epilayer design using the MAIDS mixed-level simulator. 1331-1338 - John T. Colvin, Saket S. Bhatia, Kenneth K. O:
Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology. 1339-1344 - Hiroto Matsuoka, Tsuneo Tsukahara:
A 5-GHz frequency-doubling quadrature modulator with a ring-type local oscillator. 1345-1348 - D. Abbott, Z. J. Lemnois:
Introduction to the 20th annual IEEE GaAs IC Symposium. 1179-1180 - John R. Long:
Introduction to 1998 Bipolar/BiCMOS Circuits and Technology Meeting. 1270-1271
Volume 34, Number 10, October 1999
- Siamak Mortezapour, Edward K. F. Lee:
Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter. 1350-1359 - Manuel Mota, Jorgen Christiansen:
A high-resolution time interpolator based on a delay locked loop and an RC delay line. 1360-1366 - R. Timothy Edwards, Gert Cauwenberghs:
Mixed-mode correlator for micropower acoustic transient classification. 1367-1372 - Kuang-Hu Huang, Wei-Cheng Wang, Tang-Huei Yang, Chorng-Kuang Wang:
A 2-V 7.2° jitter AM-suppression CMOS amplifier using current-mode hybrid magnitude control. 1373-1381 - Behzad Razavi:
A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs. 1382-1385 - Louis S. Y. Wong, Chee Yee Kwok, Graham A. Rigby:
A 1-V CMOS D/A converter with multi-input floating-gate MOSFET. 1386-1390 - Satoshi Utsugi, Masami Hanyu, Yoshinori Muramatsu, Tadahiko Sugibayashi:
Noncomplimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAM. 1391-1394 - Chong-Fatt Law, Samir S. Rofail, Kiat Seng Yeo:
A low-power 16×16-b parallel multiplier utilizing pass-transistor logic. 1395-1399 - Hongyan Yan, Manish Biyani, Kenneth K. O:
A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2) latch and its application in a dual-modulus prescaler. 1400-1404 - Xavier Aragonès, Antonio Rubio:
Experimental comparison of substrate noise coupling using different wafer types. 1405-1409 - Keith A. Bowman, Blanca Austin, John C. Eble, Xinghai Tang, James D. Meindl:
A physical alpha-power law MOSFET model. 1410-1414 - Shyh-Yih Ma, Liang-Gee Chen:
A single-chip CMOS APS camera with direct frame difference output. 1415-1418 - Sunderarajan S. Mohan, Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee:
Simple accurate expressions for planar spiral inductances. 1419-1424
Volume 34, Number 11, November 1999
- Anthony G. Aipperspach, David H. Allen, Dennis T. Cox, Nghia Phan, Salvatore N. Storino:
A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects. 1430-1435 - Sung Bae Park, Young Wug Kim, Young Gun Ko, Kwang Il Kim, Il Kwon Kim, Hee-Sung Kang, Jin Oh Yu, Kwang Pyuk Suh:
A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor. 1436-1445 - Jong-Woo Park, Yun-Gi Kim, Il-Kwon Kim, Kyu-Charn Park, Kyu-Chan Lee, Tae-Sung Jung:
Performance characteristics of SOI DRAM for low-power application. 1446-1453 - Ramesh Senthinathan, Stephen Fischer, Hamid Rangchi, Hadi Yazdanmehr:
A 650-MHz, IA-32 microprocessor with enhanced data streaming for graphics and video. 1454-1465 - Michael Golden, Steve Hesley, Alisa Scherer, Matthew Crowley, Scott C. Johnson, Stephan Meier, Dirk Meyer, Jerry D. Moench, Stuart F. Oberman, Hamid Partovi, Fred Weber, Scott White, Tim Wood, John Yong:
A seventh-generation x86 microprocessor. 1466-1477 - Carmine Nicoletta, Jose Alvarez, Eric Barkin, Chai-Chin Chao, Brad R. Johnson, Franklin M. Lassandro, Paresh Patel, Douglas Reid, Hector Sanchez, Joshua Siegel, Michael Snyder, Steven Sullivan, Scott A. Taylor, Minh Vo:
A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect. 1478-1491 - Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama:
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. 1492-1500 - Hector Sanchez, Joshua Siegel, Carmine Nicoletta, James P. Nissen, José Alvarez:
A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm, 3.5-nm Tox, 1.8-V CMOS technology. 1501-1511 - Gajendra P. Singh, Raoul B. Salem:
High-voltage-tolerant I/O buffers with low-voltage CMOS process. 1512-1525 - Toshiro Takahashi, Takashi Muto, Yuji Shirai, Fumihiko Shirotori, Yoshifumi Takada, Akira Yamagiwa, Akira Nishida, Atsuo Hotta, Tadashi Kiyuna:
110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock. 1526-1533 - Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui:
A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology. 1536-1543 - Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi:
A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications. 1544-1550 - Yoshikazu Miyawaki, Osamu Ishizaki, Yoshihiko Okihara, Tsutomu Inaba, Fumihiko Nitta, Masaaki Mihara, Takashi Hayasaka, Kazuo Kobayashi, Tadashi Omae, Hiroshi Kimura, Satoshi Shimizu, Hiromi Makimoto, Yoshiki Kawajiri, Masashi Wada, Hirofumi Sonoyama, Jun Etoh:
A 29-mm2, 1.8-V-only, 16-Mb DINOR flash memory with gate-protected-poly-diode (GPPD) charge pump. 1551-1556 - Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka:
A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. 1557-1563 - Cangsang Zhao, Uddalak Bhattacharya, Martin Denham, Jim Kolousek, Yi Lu, Yong-Gee Ng, Novat Nintunze, Kamal Sarkez, Hemmige D. Varadarajan:
An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin. 1564-1570 - Hirotoshi Sato, Tomohisa Wada, Shigeki Ohbayashi, Kunihiko Kozaru, Yasuyuki Okamoto, Yoshiko Higashide, Tadayuki Shimizu, Yukio Maki, Rui Morimoto, Hisakazu Otoi, Tsuyoshi Koga, Hiroki Honda, Makoto Taniguchi, Yutaka Arita, Toru Shiomi:
A 500-MHz pipelined burst SRAM with improved SER immunity. 1571-1579 - Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman:
A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. 1580-1588 - Hongil Yoon, Gi-Won Cha, Changsik Yoo, Nam-Jong Kim, Keum-Yong Kim, Chang Ho Lee, Kyu-Nam Lim, Kyuchan Lee, Jun-Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae-Young Chung, Kinam Kim, Soo-In Cho:
A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. 1589-1599 - Satoru Takase, Natsuki Kushiyama:
A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme. 1600-1606 - Masakazu Suzuoki, Ken Kutaragi, Toshiyuki Hiroi, Hidetaka Magoshi, Shin'ichi Okamoto, Masaaki Oka, Akio Ohba, Yasuyuki Yamamoto, Makoto Furuhashi, Masayoshi Tanaka, Teiji Yutaka, Toyoshi Okada, Masato Nagamatsu, Yukihiro Urakawa, Masami Funyu, Atsushi Kunimatsu, Harutaka Goto, Kazuhiro Hashimoto, Nobuhiro Ide, Hiroaki Murakami, Yukio Ohtaguro, Akira Aono:
A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder. 1608-1618 - Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada:
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. 1619-1626 - Michel Harrand, Jose Sanches, Alain Bellon, Joseph Bulone, Alain Tournier, Olivier Deygas, Jean-Claude Herluison, David Doise, Elisabeth Berrebi:
A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller. 1627-1633 - Alan Y. Kwentus, Patrick Pai, Steven Jaffe, Ray Gomez, Shauhyuarn Sean Tsai, Tom Kwan, Hing T. Hung, Young J. Shin, Vin Hue, Darwin Cheung, Raheel A. Khan, Christopher M. Ward, Mong-Kai Ku, Kenneth Choi, Jim Searle, Klaas Bult, Kelly B. Cameron, Jason Demas, Charles Reames, Henry Samueli:
A single-chip universal digital satellite receiver with 480-MHz IF input. 1634-1646 - Lionel J. D'Luna, Loke Tan, Dean W. Mueller, Joe L. Laskowski, Kelly B. Cameron, Jind-Yeh Lee, David Gee, Jason S. Monroe, Honman S. Law, Jason Chang, Myles H. Wakayama, Tom Kwan, Chi-Hung Lin, Aaron Buchwald, Tarek Kaylani, Fang Lu, Tom Spieker, Robert A. Hawley, Henry Samueli:
A single-chip universal cable set-top box/modem transceiver. 1647-1660 - Bryan E. Bloodworth, Patrick P. Siniscalchi, Geert A. De Veirman, Andrija Jezdic, Richard Pierson, Raj Sundararaman:
A 450-Mb/s analog front end for PRML read channels. 1661-1675 - Narendra Rao, Vishnu Balan, R. Contreras:
A 3-V, 10-100-MHz continuous-time seventh-order 0.05° equiripple linear phase filter. 1676-1682 - J. Pathak:
Introduction to the memory section. 1534-1535 - S. Molloy:
Introduction to the signal processing section. 1607
Volume 34, Number 12, December 1999
- Paul Hurst, Fritz Kub, John M. Khoury:
Guest editorial. 1688-1690 - Hiroshi Yamazaki, Kazuaki Oishi, Kunihiko Gotoh:
An accurate center frequency tuning scheme for 450-KHz CMOS Gm-C bandpass filters. 1691-1697 - Venu Gopinathan, Maurice Tarsia, Davy Choi:
Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in submicrometer CMOS. 1698-1707 - Geert Van der Plas, Jan Vandenbussche, Willy Sansen, Michel S. J. Steyaert, Georges G. E. Gielen:
A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. 1708-1718 - Alex R. Bugeja, Bang-Sup Song, Patrick L. Rakers, Steven F. Gillig:
A 14-b, 100-MS/s CMOS DAC designed for spectral performance. 1719-1732 - Axel Thomsen, Dan B. Kasha, Lei Wang, Wai L. Lee:
A 110-dB-THD, 18-mW DAC using sampling of the output and feedback to reduce distortion. 1733-1740 - Hai Tao, John M. Khoury:
A 400-Ms/s frequency translating bandpass sigma-delta modulator. 1741-1752 - Jürgen A. E. P. van Engelen, Rudy J. van de Plassche, Eduard Stikvoort, Ardie G. Venes:
A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF. 1753-1764 - Ardeshir Namdar, Bosco H. Leung:
A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop. 1765-1776 - Susanne A. Paul, Hae-Seung Lee, John Goodrich, Titiimaea F. Alailima, Daniel D. Santiago:
A Nyquist-rate pipelined oversampling A/D converter. 1777-1787 - Brian P. Brandt, Joseph Lutsky:
A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist. 1788-1795 - Gian Hoogzaad, Raf L. J. Roovers:
A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist ADC in 0.8 mm2. 1796-1802 - Hendrik van der Ploeg, Robert Remmers:
A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS. 1803-1811 - Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis:
A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD. 1812-1820 - David X. D. Yang, Abbas El Gamal, Boyd Fowler, Hui Tian:
A 640×512 CMOS image sensor with ultrawide dynamic range floating-point pixel-level ADC. 1821-1834 - Masayuki Furumiya, Keisuke Hatano, Yasutaka Nakashiba, Ichiro Murakami, Tohru Yamada, Takashi Nakano, Yukiya Kawakami, Toru Kawasaki, Yasuaki Hokari:
A 1/2-in, 1.3 M-pixel progressive-scan CCD image sensor employing 0.25-μm gap single-layer poly-Si electrodes. 1835-1842 - Masayuki Furumiya, Keisuke Hatano, Yasutaka Nakashiba, Ichiro Murakami, Tohru Yamada, Takashi Nakano, Yukiya Kawakami, Toru Kawasaki, Yasuaki Hokari:
A 2D CMOS microfluxgate sensor system for digital detection of weak magnetic fields. 1843-1851 - Satoshi Shigematsu, Hiroki Morimura, Yasuyuki Tanabe, Takuya Adachi, Katsuyuki Machida:
A single-chip fingerprint sensor and identifier. 1852-1859 - Nicolò Manaresi, Roberto Rambaldi, Marco Tartagni, Zsolt Miklós Kovács-Vajna, Roberto Guerrieri:
A CMOS-only micro touch pointer. 1860-1868 - Paolo Orsatti, Francesco Piazza, Qiuting Huang:
A 20-mA-receive, 55-mA-transmit, single-chip GSM transceiver in 0.25-μm CMOS. 1869-1880 - Werner Simbürger, Hans-Dieter Wohlmuth, Peter Weger, Alexander Heinz:
A monolithic transformer coupled 5-W silicon power amplifier with 59% PAE at 0.9 GHz. 1881-1892 - Aarno Pärssinen, Jarkko Jussila, Jussi Ryynänen, Lauri Sumanen, Kari A. I. Halonen:
A 2-GHz wide-band direct conversion receiver for WCDMA applications. 1893-1903 - Marc A. F. Borremans, Carl De Ranter, Michel S. J. Steyaert:
A CMOS dual-channel, 100-MHz to 1.1-GHz transmitter for cable applications. 1904-1913 - Yuriy M. Greshishchev, Peter Schvan:
A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier. 1914-1920 - Eiji Oki, Naoaki Yamanaka, Yusuke Ohtomo, Kazuhiko Okazaki, Ryusuke Kawano:
A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration. 1921-1934 - Johann-Christoph Scheytt, Gerhard Hanke, Ulrich Langmann:
A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems. 1935-1943 - Eduard Säckinger, Yusuke Ota, Thaddeus J. Gabara, Wilhelm C. Fischer:
A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection. 1944-1950 - Patrik Larsson:
A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability. 1951-1960 - Michael Moyal, Martin Groepl, Thomas Blon:
A 25-kft, 768-kb/s CMOS analog front end for multiple-bit-rate DSL transceiver. 1961-1972 - Richard K. Hester, Subhashish Mukherjee, Darryl Padgett, Donald Richardson, William Bright, Maher M. Sarraj, Joseph T. Nabicht, Michael D. Agah, Abdellatif Bellaouar, Irfan Chaudhry, James R. Hellums, Kazi Islam, Arash Loloee, Ching-Yuh Tsay, Glenn H. Westphal:
CODEC for echo-canceling, full-rate ADSL modems. 1973-1985
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