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ORCIDESSCIRC 2003: Estoril, Portugal
- José E. Franca, Rudolf Koch:
ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003. IEEE 2003, ISBN 0-7803-7995-0 - Kenneth Martin:
Complex signal processing is not - complex. 3-14 - Dennis M. Monticelli:
Taking a system approach to energy management. 15-19 - Josef Fenk:
RF-trends in mobile communication. 21-27 - Eugenio Cantatore, E. J. Meijer:
Transistor operation and circuit performance in organic electronics. 29-36 - Gerhard Muller, Nicolas Nagel, Cay-Uwe Pinnow, Thomas Roehr:
Emerging non-volatile memory technologies. 37-44 - Takashi Yoshimori:
IP related activities in Toshiba and Japanese SoC industries. 45-48 - Christian Panis, Michael Bramberger, Herbert Grünbacher, Jari Nurmi
:
A scaleable instruction buffer for a configurable DSP core. 49-52 - Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Hoi-Jun Yoo:
A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals. 53-56 - Joong-Seok Moon, Taek-Jun Kwon, Jeff Sondeen, Jeffrey Draper:
An area-efficient standard-cell floating-point unit design for a processing-in-memory system. 57-60 - Gustavo Liñán Cembrano, Ángel Rodríguez-Vázquez, Rafael Castro-López, Servando Espejo-Meana:
A 1000FPS@128×128 vision processor with 8-bit digitized I/O. 61-64 - Teruyasu Taguchi, Makoto Ogawa, Tadashi Shibata:
An analog image processing LSI employing scanning line-parallel processing. 65-68 - Milutin Stanacevic, Gert Cauwenberghs:
Micropower mixed-signal acoustic localizer. 69-72 - Marc Tiebout:
A 50 GHz direct injection locked oscillator topology as low power frequency divider in 0.13 μm CMOS. 73-76 - Hans-Dieter Wohlmuth, Daniel Kehrer:
A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOS. 77-80 - Hesham Ahmed, Christopher A. DeVries, Ralph Mason:
A digitally tuned 1.1 GHz subharmonic injection-locked VCO in 0.18μm CMOS. 81-84 - Johan Sommarek, Jouko Vankka, Jaakko Ketola, Ilari Teikari, Kari Halonen:
A digital quadrature modulator with on-chip D/A converter. 85-88 - Kevin O'Sullivan, Chris Gorman, Michael Hennessy, Vincent Callaghan:
A 12b 320 MSample/s current-steering CMOS D/A converter in 0.44mm2. 89-92 - Jurgen Deveugele, Pieter Palmers, Michiel Steyaert:
Single-side-band digital-to-analog converters for Nyquist signal generation. 93-96 - Han-Il Lee, Je-Kwang Cho, Kun-Seok Lee, In-Chul Hwang, Tae-Won Ahn, Kyung-Suc Nah, Byeong-Ha Park:
A Σ-Δ fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications. 97-100 - Amr M. Fahim:
A compact, low-power low-jitter digital PLL. 101-104 - Adrian Maxim:
A low voltage, 10-2550MHz, 0.15μ CMOS, process and divider modulus independent PLL using zero-VT MOSFETs. 105-108 - Gerry C. T. Leung, Howard C. Luong:
A 1-V 13-mW 2.5-GHz double-rate phase-locked loop with phase alignment for zero delay. 109-112 - Gerry C. T. Leung, Howard C. Luong:
A 1-V 5.2-GHz 27.5-mW fully-integrated CMOS WLAN synthesizer. 113-116 - Roger Steadman, Armin Kemna, Francisco Morales Serrano, Gereon Vogtmeier, Erol Özkan, Werner Brockherde, Bedrich J. Hosticka:
A CMOS photodiode array with in-pixel data acquisition system. 117-120 - Jose G. Rocha, N. F. Ramos, Reinoud F. Wolffenbuttel, José Higino Correia:
CMOS x-ray image sensor with pixel level A/D conversion. 121-124 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A smart image sensor with high-speed feeble ID-beacon detection for augmented reality system. 125-128 - Kuan-Hsun Huang, Li-Ju Lin, Chung-Yu Wu:
A CMOS focal-plane rotation sensor with retinal processing circuit. 129-132 - Murat Tepegoz, Tayfun Akin:
A readout circuit for QWIP infrared detector arrays using current mirroring integration. 133-136 - Vladimir Aparin, Lawrence E. Larson:
Linearization of monolithic LNAs using low-frequency low-impedance input termination. 137-140 - Adiseno, Håkan Magnusson, Håkan K. Olsson:
A 1.8-V wide-band CMOS LNA for multiband multistandard front-end receiver. 141-144 - Rony E. Amaya, Calvin Plett:
Design of high gain fully-integrated distributed amplifiers in 0.35 μm CMOS. 145-148 - Luiz M. Franca-Neto, Bradley A. Bloechel, Krishnamurthy Soumyanath:
17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18μm logic CMOS technology. 149-152 - Mihai A. T. Sanduleanu, Eduard Stikvoort:
Inductor-less, 10Gb/s limiter with 10mV sensitivity and offset/temperature compensation in baseline CMOS18. 153-156 - Andrea Gerosa, Andrea Maniero, Andrea Neviani:
A fully-integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakers. 157-160 - Jonny Johansson, Harald Neubauer, Hans Hauer:
A 16-bit 60μW multi-bit ΣΔ modulator for portable ECG applications. 161-164 - Lourans Samid, Yiannos Manoli:
A micro power continuous-time ΣΔ modulator. 165-168 - João Risques, Jorge Duarte, Vasco Amaro, Seng-Pan U, Kuok Vai Chiang, Ka Fai Chang, Keng Chong Lai:
A very area/power efficient mixed signal circuit for voice signal processing in 0.18 digital technology. 169-172 - R. Peck, Dietmar Schroeder:
A low-power entropy-coding analog/digital converter with integrated data compression. 173-176 - Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija:
Energy minimization method for optimal energy-delay extraction. 177-180 - Naran Sirisantana, Kaushik Roy:
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies. 181-184 - Manish Garg:
High performance pipelining method for static circuits using heterogeneous pipelining elements. 185-188 - Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada:
A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design. 189-192 - Mohamed M. Hafed, Gordon W. Roberts:
An 8-channel, 12-bit, 20 MHz fully differential tester IC for analog and mixed-signal circuits. 193-196 - Bin Wu, Yue-Hong Sutu, Karthik Ramamurthy, Dong Zheng, Eugene Cheung, Toan Tran, Yong Jiang, Manoj Rana:
A serial 10 gigabit Ethernet transceiver on digital 0.13μm CMOS. 197-200 - Francesco Adduci, Marzia Annovazzi, Gianluigi Boarin, A. Colaci, Vittorio Colonna, Gabriele Gandolfi, Michele Sala, Fabrizio Salidu, Fabrizio Stefani, Martin Frey, P. Kirchlechner, Christian Kutschenreiter, Andrea Baschirotto:
A DSP-based digital IF AM/FM car-radio receiver. 201-204 - Anders Berkeman, Viktor Öwall:
Custom silicon implementation of a delayless acoustic echo canceller algorithm. 205-208 - Floriberto A. Lima, J. N. Ramalho, D. Tavares, J. Duarte, C. Albuquerque, T. Marques, A. Geraldes, A. P. Casimiro, Gert Renkema, J. Been, Wouter Groeneveld:
A novel universal battery charger for NiCd, NiMH, Li-ion and Li-polymer. 209-212 - Pui-Lam Siu, Chiu-Sing Choy, Chi Fat Chan, Kong-Pang Pun:
A contactless smartcard designed with asynchronous circuit technique. 213-216 - Edmund Götz, Hans Krobel, Gunter Marzinger, Bernd Memmler, Christian Muenker, Burkhard Neurauter, Dirk Romer, Jorn Rubach, Werner Schelmbauer, Markus Scholz, Martin Simon, Ulrich Steinacker, Claus Stoger:
A quad-band low power single chip direct conversion CMOS transceiver with ΣΔ-modulation loop for GSM. 217-220 - Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis, Nikos Haralabidis:
A single-chip, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, 0.18μm CMOS RF transceiver for 802.11a/b/g wireless LAN. 221-224 - Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee, Donghyeon Seo, Inho Song, Sanghun Jung, Joonbae Park, Deog-Kyoon Jeong, Wonchan Kim:
A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b. 225-228 - Thomas Rühlicke, Markus Zannoth, Bernd-Ulrich Klepser:
A highly integrated, dual-band, multi-mode wireless LAN transceiver. 229-232 - Antonio Di Giandomenico, Susana Patón, Andreas Wiesbauer, Luis Hernández, Thomas Pötscher, Lukas Dörrer:
A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS. 233-236 - Amir Hadji-Abdolhamid, David Andrew Johns:
A 400-MHz 6-bit ADC with a partial analog equalizer for coaxial cable channels. 237-240 - Amir Zjajo, Hendrik van der Ploeg, Maarten Vertregt:
A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μm CMOS. 241-244 - Lukas Dörrer, Franz Kuttner, Andreas Wiesbauer, Antonio Di Giandomenico, Thomas Hartig:
10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 μm CMOS process. 245-248 - Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback. 249-252 - Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen:
Modelling impact of digital substrate noise on embedded regenerative comparators. 253-256 - Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. 257-260 - Atul Katoch, Sanjeev K. Jain, Maurice Meijer:
Aggressor aware repeater circuits for improving on-chip bus performance and robustness. 261-264 - Himanshu Kaul, Dennis Sylvester, David T. Blaauw:
Clock net optimization using active shielding. 265-268 - Theo G. S. M. Rijks, Joost T. M. van Beek, M. J. E. Ulenaers, Jeroen De Coster, Robert Puers, Arnold J. den Dekker, L. van Teeffelen:
Passive integration and RF MEMS: a toolkit for adaptive LC circuits. 269-272 - Enrico Dallago, Alberto Danioni, Giulio Ricotti, Giuseppe Venchi:
Single chip, low supply voltage piezoelectric transformer controller. 273-276 - Ting Huang, Zhigong Wang, En Zhu, Xiaoming Wang, Mingzhen Xiong:
24 Gb/s laser/modulator driver IC using 0.2μm gate length PHEMTs. 277-280 - Harish S. Muthali, Thomas P. Thomas, Ian A. Young:
A CMOS 10Gb/s SONET transceiver. 281-284 - Rui Tao, Manfred Berroth:
10 Gb/s CMOS limiting amplifier for optical links. 285-287 - Chia-Ming Tsai, Li-Ren Huang, Day-Uei Li, Chien-Fu Chang:
10 Gb/s single-ended laser driver in 0.35μm SiGe BiCMOS technology. 289-292 - Maxim Pribytko, Patrick J. Quinn:
A CMOS single-ended OTA with high CMRR. 293-296 - Libin Yao, Michiel Steyaert, Willy Sansen:
A 0.8-V, 8-μW, CMOS OTA with 50-dB gain and 1.2-MHz GBW in 18-pF load. 297-300 - Ryutaro Saito, Kinya Hosoda, Akira Hyogo, Takaya Maruyama, Hiroshi Komuraki, Hisayasu Sato, Keitaro Sekine:
A 1.8-V 73-dB dynamic-range CMOS variable gain amplifier. 301-304 - Tobias Gemmeke, Michael Gansen, Thomas G. Noll, Heinrich J. Stockmanns:
Optimization of device dimensions for high-performance low-power architecture blocks. 305-308 - Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown:
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology. 309-312 - Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown:
Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. 313-316 - Mindaugas Drazdziulis, Per Larsson-Edefors:
A gate leakage reduction strategy for future CMOS circuits. 317-320 - Radu Zlatanovici, Borivoje Nikolic:
Power-performance optimal 64-bit carry-lookahead adders. 321-324 - Jan Nissinen, Pasi Palojärvi, Juha Kostamovaara:
A CMOS receiver for a pulsed time-of-flight laser rangefinder. 325-328 - Diego Barrettino, Wan Ho Song, Markus Graf, Andreas Hierlemann, Henry Baltes:
A micro-hotplate-based monolithic CMOS thermal analysis system. 329-332 - Olaf M. Schrey, O. Elkhalili, Peter Mengel, M. Petermann, Werner Brockherde, Bedrich J. Hosticka:
A 4×64 pixel CMOS image sensor for 3D measurement applications. 333-336 - G. Laurent, Luis Moreno Hagelsieb, Dimitri Lederer, P. E. Lobert, Denis Flandre, J. Remacle, Jean-Pierre Raskin:
DNA electrical detection based on inductor resonance frequency in standard CMOS technology. 337-340 - Robert Swoboda, Horst Zimmermann:
A low-noise 1.8Gbps bipolar OEIC. 341-344 - Hugo Veenstra, Edwin van der Heijden:
A 19-23 GHz integrated LC-VCO in a production 70 GHz fT SiGe technology. 349-352 - Laurent Perraud, Jean-Louis Bonnot, Nicolas Sornin, Christophe Pinatel:
Fully integrated 10 GHz CMOS VCO for multi-band WLAN applications. 353-356 - Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Mohamed Talbi, Asit Ray, Lawrence F. Wagner:
A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology. 357-360 - Wei-Zen Chen, Chien-Liang Kuo, Chia-Chun Liu:
10 GHz quadrature-phase voltage controlled oscillator and prescaler. 361-364 - João Ramos, Xiaohong Peng, Michiel Steyaert, Willy Sansen:
Three stage amplifier frequency compensation. 365-368 - Philippe Coppejans, Michiel Steyaert:
Dynamic biasing: a low power linearisation technique. 369-372 - Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal, Chad Lackey:
1.5V rail-to-rail programmable-gain CMOS amplifier. 373-376 - Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín:
Input/output rail-to-rail video op-amp with constant behaviour over the entire voltage range. 377-380 - Franz Schlögl, Horst Zimmermann:
Opamp with 106 dB DC gain in 120nm digital CMOS. 381-384 - Daniel Kehrer, Hans-Dieter Wohlmuth:
A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 μm CMOS. 385-388 - Wen-Hu Zhao, Zhi-Gong Wang, En Zhu:
A 3.125-Gb/s CMOS word alignment demultiplexer for serial data communications. 389-392 - Alistair Lee McEwan, Syed Ahmar Shah, Steve Collins:
A direct digital frequency synthesis system for low power communications. 393-396 - Antonio Giuseppe Maria Strollo, Davide De Caro, Ettore Napoli, Nicola Petra:
Direct digital frequency synthesis with dual-slope approach. 397-400 - Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson:
Bitline leakage equalization for sub-100nm caches. 401-404 - Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka:
A novel hierarchical multi-port cache. 405-408 - Bernhard Wicht, Thomas Nirschl, Doris Schmitt-Landsiedel:
A yield-optimized latch-type SRAM sense amplifier. 409-412 - Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne P. Burleson, Ram Krishnamurthy, Shekhar Borkar:
Low voltage sensing techniques and secondary design issues for sub-90nm caches. 413-416 - Thierry Melly, Erwan Le Roux, David Ruffieux, Vincent Peiris:
A 0.6mA, 0.9V 100MHz FM front-end in a 0.18μm CMOS-D technology. 417-420 - Kari Stadius, Arto Malinen, Petri Järviö, Kari Halonen, Petteri Paatsila:
A cable-modem RF tuner. 421-424 - P. Jacobs, Johan Janssens, Tomas Geurts, Jan Crols:
A 0.35μ CMOS fractional-N transmitter for 315/433/868/915 MHz ISM applications. 425-428 - Nicolas Schlumpf, Michel J. Declercq, Catherine Dehollain:
A fast modulator for dynamic supply linear RF power amplifier. 429-432 - Helen Waite, P. Ta, Jennie Chen, H. Li, M. Gao, C. S. Chang, Y. S. Chang, William Redman-White, Olivier Charlon, Y. Fan, R. Perkins, D. Brunel, E. Soudee:
A CDMA2000 zero IF receiver with low-leakage integrated front-end. 433-436 - Concepción Aldea, Santiago Celma, Aránzazu Otín:
A 62 dB dynamic range sixth-order band pass filter with 100-175 MHz tuning range. 437-440 - Robert Rieger, Andreas Demosthenous, John Taylor:
Continuously tunable, very long time constant CMOS integrator for a neural recording implant. 441-444 - Heikki Repo, Timo Rahkonen:
Programmable switched capacitor 4-tap FIR filter. 445-448 - Shinichi Hori, Tadashi Maeda, Hitoshi Yano, Noriaki Matsuno, Keiichi Numata, Nobuhide Yoshida, Yuji Takahashi, Tomoyuki Yamase, Robert Walkington, Hikaru Hikaru:
A widely tunable CMOS Gm-C filter with a negative source degeneration resistor transconductor. 449-452 - Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks. 453-456 - Manuel Innocent, Piet Wambacq, Stéphane Donnay, Willy Sansen, Hugo De Man:
A linear high voltage charge pump for MEMs applications in 0.18μm CMOS technology. 457-460 - Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output buffer. 461-464 - Simone Tisa, A. Lotito, Andrea Carlo Giudice, Franco Zappa:
Monolithic time-to-digital converter with 20ps resolution. 465-468 - Ilkka Nissinen, Antti Mäntyniemi, Juha Kostamovaara:
A CMOS time-to-digital converter based on a ring oscillator for a laser radar. 469-472 - Martin Anderson, Jonas Elbornsson, Jan-Erik Eklund, Joakim Alvbrant, Henrik Fredriksson:
Verification of a blind mismatch error equalization method for randomly interleaved ADCs using a 2.5V/12b/30MSs PSAADC. 473-476 - Hitoshi Tani, Yoshihisa Fujimoto, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto:
A low power sample-and-hold amplifier. 477-480 - Albert Jan Huitsing, Theo Smedes, H.-U. Schröder:
A simple design methodology for increased ESD robustness of CMOS core cells. 481-484 - Emmanuel M. Drakakis:
A 1mW 40-190MHz BJT logarithmic biquad. 485-488