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ORCIDIEEE Journal of Solid-State Circuits, Volume 37
Volume 37, Number 1, January 2002
- Omid Oliaei, Patrick Clément, Philippe Gorisse:
A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE. 2-10 - Tai-Haur Kuo, Kuan-Dar Chen, Horng-Ru Yeng:
A wideband CMOS sigma-delta modulator with incremental data weighted averaging. 11-17 - Daniel R. McMahill, Charles G. Sodini:
A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated Σ-Δ frequency synthesizer. 18-26 - Hussain A. Alzaher, Hassan O. Elwan, Mohammed Ismail:
A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers. 27-37 - Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino:
Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. 38-50 - Oscal T.-C. Chen, Robin Ruey-Bin Sheen:
A power-efficient wide-range phase-locked loop. 51-62 - Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang:
Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. 63-76 - Snezana Jenei, Bart K. J. C. Nauwelaers
, Stefaan Decoutere:
Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors. 77-80 - Arne E. Buck, Charles L. McDonald, Stephen H. Lewis, T. R. Viswanathan:
A CMOS bandgap reference without resistors. 81-83 - Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura:
Circuit techniques for a 1.8-V-only NAND flash memory. 84-89 - Amr M. Fahim, Mohamed I. Elmasry:
Low-power high-performance arithmetic circuits and architectures. 90-94 - Ming-Hwa Sheu, Su-Hon Lin:
Fast compensative design approach for the approximate squaring function. 95-97
Volume 37, Number 2, February 2002
- Bernhard E. Boser:
Editorial. 103 - Bernhard E. Boser:
New associate editor. 104 - Michael Q. Le, Paul J. Hurst, John P. Keane:
An adaptive analog noise-predictive decision-feedback equalizer. 105-113 - Pietro Andreani, Sven Mattisson:
On the use of Nauta's transconductor in low-frequency CMOS gm-C bandpass filters. 114-124 - Bogdan Pankiewicz, Marek Wójcikowski, Stanislaw Szczepanski, Yichuang Sun:
A field programmable analog array for CMOS continuous-time OTA-C filter applications. 125-136 - Koen L. R. Mertens, Michiel S. J. Steyaert:
A 700-MHz 1-W fully differential CMOS class-E power amplifier. 137-141 - Philippe Maige, Yannick Guédon:
A class-D vertical booster for CRT. 142-150 - Zoran B. Randjelovic, Maher Kayal, Radevoje Popovic, Hubert Blanchard:
Highly sensitive Hall magnetic sensor microsystem in CMOS technology. 151-159 - Massimo Barbaro, Pierre-Yves Burgi, Alessandro Mortara, Pascal Nussbaum, Friedrich Heitger:
A 100×100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding. 160-172 - Dirk Droste, Josef Bille:
An ASIC for Hartmann-Shack wavefront detection. 173-182 - Keith A. Bowman, Steven G. Duvall, James D. Meindl:
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. 183-190 - Se-Joong Lee, Hoi-Jun Yoo:
Race logic architecture (RALA): a novel logic concept using the race scheme of input variables. 191-201 - David J. Kinniment, Alexandre V. Bystrov, Alex Yakovlev:
Synchronization circuit performance. 202-209 - Masayuki Miyazaki, Goichi Ono, Koichiro Ishibashi:
A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias. 210-217 - Hans Jürgen Mattausch, Takayuki Gyohten, Yoshihiro Soda, Tetsushi Koide:
Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. 218-227 - Samuel A. Steidl, John F. McDonald:
A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology. 228-236 - Seong-Mo Yim, Tong Chen, Kenneth K. O:
The effects of a ground shield on the characteristics and performance of spiral inductors. 237-244 - Jae-Yoon Sim, Jang-Jin Nam, Young-Soo Sohn, Hong-June Park, Chang-Hyun Kim, Soo-In Cho:
A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme. 245-250 - Jae-Kyung Wee, Kyeong-Sik Min, Jong-Tai Park, Sang-Pil Lee, Young-Hee Kim, Tae-Heum Yang, Jong-Doo Joo, Jin-Yong Chung:
A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs. 251-254 - Bendik Kleveland, Carlos H. Diaz, Dieter Vook, Liam Madden, Thomas H. Lee, S. Simon Wong:
Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design". 255
Volume 37, Number 3, March 2002
- Jorge Grilo, Ian Galton, Kevin J. Wang, Raymond Montemayor:
A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver. 271-278 - Ovidiu Bajdechi, Johan H. Huijsing:
A 1.8-V ΔΣ modulator interface for an electret microphone with on-chip reference. 279-285 - Troy Stockstad, Hirokazu Yoshizawa:
A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier. 286-292 - Troy Stockstad, Hirokazu Yoshizawa:
A 40-μA/channel compensated 18-channel strain gauge measurement system for stress monitoring in dental implants. 293-301 - Iuri Mehr, Prabir C. Maulik, Donald Paterson:
A 12-bit integrated analog front end for broadband wireline networks. 302-309 - David J. Foley, Michael P. Flynn:
A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS. 310-316 - Kamran Azadet, Erich F. Haratsch, Helen Kim, Fadi Saibi, Jeffrey H. Saunders, Michael Shaffer, Leilei Song, Meng-Lin Yu:
Equalization and FEC techniques for optical transceivers. 317-327 - Bernd-Ulrich H. Klepser, Markus Scholz, Edmund Götz:
A 10-GHz SiGe BiCMOS phase-locked-loop frequency synthesizer. 328-335 - Anne Spataro, Yann Deval, Jean-Baptiste Bégueret, Pascal Fouillat:
A VLSI CMOS delay oriented waveform converter for polyphase frequency synthesizer. 336-341 - Pietro Andreani, Henrik Sjöland:
Tail current noise suppression in RF CMOS VCOs. 342-348 - Shin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz:
Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation. 349-356 - Atsushi Yoshizawa, Yannis P. Tsividis:
Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers. 357-364 - Uma Chilakapati, Terri S. Fiez, Aria Eshraghi:
A CMOS transconductor with 80-dB SFDR up to 10 MHz. 365-370 - Ichiro Aoki, Scott D. Kee, David B. Rutledge, Ali Hajimiri:
Fully integrated CMOS power amplifier design using the distributed active-transformer architecture. 371-383 - Roberto Aparicio, Ali Hajimiri:
Capacity limits and matching properties of integrated capacitors. 384-393 - Hasnain Lakdawala, Xu Zhu, Hao Luo, Suresh Santhanam, L. Richard Carley, Gary K. Fedder:
Micromachined high-Q inductors in a 0.18-μm copper interconnect low-k dielectric CMOS process. 394-403 - Andrew J. Blanksby, Chris J. Howland:
A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder. 404-412 - Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai:
VTH-hopping scheme to reduce subthreshold leakage for low-power processors. 413-419 - W. Rhett Davis, Ning Zhang, Kevin Camera, Dejan Markovic, Tina Smilkstein, M. Josie Ammer, Engling Yeo, Stephanie Augsburger, Borivoje Nikolic, Robert W. Brodersen:
A design environment for high-throughput low-power dedicated signal processing systems. 420-431 - Conor Donovan, Michael P. Flynn:
A "digital" 6-bit ADC in 0.25-μm CMOS. 432-437 - Johan D. van der Tang, Dieter Kasperkovitz, Arthur H. M. van Roermund:
A 9.8-11.5-GHz quadrature ring oscillator for optical receivers. 438-442 - Salvatore Cosentino, Pietro Filoramo, Angelo Granata, Marco Marletta, Giuseppe Martino, Roberto Pelleriti, Felice Torrisi, Mario Paparo, Gaetano Cosentino, Piero Vita, Giuseppe Palmisano:
An integrated RF transceiver for DECT application. 443-449 - Satoshi Kumaki, Hidehiro Takata, Yoshihide Ajioka, Tsukasa Ooishi, Kazuya Ishihara, Atsuo Hanami, Takaharu Tsuji, Tetsuya Watanabe, Chikayoshi Morishima, Tomoaki Yoshizawa, Hidenori Sato, Shin-ichi Hattori, Atsushi Koshio, Kazuhiro Tsukamoto, Tetsuya Matsumura:
A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system. 450-454
Volume 37, Number 4, April 2002
- Chi-Wa Lo, Howard Cam Luong:
A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications. 459-470 - Chih-Chun Tang, Chia-Hsin Wu, Shen-Iuan Liu:
Miniature 3-D inductors in standard CMOS process. 471-480 - Frank Ellinger, Rolf Vogt, Werner Bächtold:
Ultracompact reflective-type phase shifter MMIC at C-band with 360° phase-control range for smart antenna combining. 481-486 - Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura:
A low-impedance open-bitline array for multigigabit DRAM. 487-498 - Mohamed M. Hafed, Nazmy Abaskharoun, Gordon W. Roberts:
A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits. 499-514 - Woogeun Rhee, Biagio Bisanti, Akbar Ali:
An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution. 515-520 - Chih-Ming Hung, Kenneth K. O:
A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop. 521-525 - Ka Nang Leung, Philip K. T. Mok:
A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device. 526-530
Volume 37, Number 5, May 2002
- Masakazu Yamashina, Shekhar Y. Borkar:
Guest editorial. 535 - Yido Koo, Hyungki Huh, Yongsik Cho, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems. 536-542 - Brian A. Floyd, Chih-Ming Hung, Kenneth K. O:
Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters. 543-552 - Takafumi Yamaji, Nobuo Kanou, Tetsuro Itakura:
A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range. 553-558 - Shiro Dosho, Takashi Morie, Hirokuni Fujiyama:
A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process. 559-565 - Ayman Shabra, Hae-Seung Lee:
Oversampled pipeline A/D converters with mismatch shaping. 566-578 - Theerachet Soorapanth, S. Simon Wong:
A 0-dB IL 2140±30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS. 579-586 - Daisaburo Takashima, Hiroaki Nakano:
A cell transistor scalable DRAM array architecture. 587-591 - Shoichiro Kawashima, Toru Endo, Akira Yamamoto, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Keizo Morita, Masaki Aoki:
Bitline GND sensing technique for low-voltage operation FeRAM. 592-598 - Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi:
A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit. 599-604 - Mitsuru Hiraki, Takayasu Ito, Atsushi Fujiwara, Taichi Ohashi, Tetsuro Hamano, Takaaki Noda:
A 63-μW standby power microcontroller with on-chip hybrid regulator scheme. 605-611 - Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo:
A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. 612-623 - Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. 624-632 - Atila Alvandpour, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A sub-130-nm conditional keeper technique. 633-638 - Jaeha Kim, Mark A. Horowitz:
An efficient digital sliding controller for adaptive power-supply regulation. 639-647 - Chulwoo Kim, Sung-Mo Kang:
A low-swing clock double-edge triggered flip-flop. 648-652 - Peter J. Vancorenland, Michiel S. J. Steyaert:
A 1.57-GHz fully integrated very low-phase-noise quadrature VCO. 653-656 - Johan van der Tang, Pepijn van de Ven, Dieter Kasperkovitz, Arthur H. M. van Roermund:
Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator. 657-661 - Shahram Mahdavi, Asad A. Abidi:
Fully integrated 2.2-mW CMOS front end for a 900-MHz wireless receiver. 662-669
Volume 37, Number 6, June 2002
- Shang-Yuan (Sean) Chuang, Terry L. Sculley:
A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. 674-683 - Alireza Shirvani, David K. Su, Bruce A. Wooley:
A CMOS RF power amplifier with parallel amplification for efficient power control. 684-693 - Ming-Chou Chiang, Shey-Shi Lu, Chin-Chun Meng, Shih-An Yu, Shih-Cheng Yang, Yi-Jen Chan:
Analysis, design, and optimization of InGaP-GaAs HBT matched-impedance wide-band amplifiers with multiple feedback loops. 694-701 - Sander L. J. Gierkink, Ed van Tuijl:
A coupled sawtooth oscillator combining low jitter with high control linearity. 702-710 - Xavier Maillard, Frédéric Devisch, Maarten Kuijk:
A 900-Mb/s CMOS data recovery DLL using half-frequency clock. 711-715 - Bendik Kleveland, Xiaoning Qi, Liam Madden, Takeshi Furusawa, Robert W. Dutton, Mark A. Horowitz, S. Simon Wong:
High-frequency characterization of on-chip digital interconnects. 716-725 - Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, Joo-Hwan Cho, Pil Soo Lee, Jin-Hong Ahn, Jin-Yong Chung:
A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM. 726-734 - Nobutaro Shibata, Mayumi Watanabe, Yasuyuki Tanabe:
A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell. 735-750 - Douglas J. Fouts, Phillip E. Pace, Christopher Karow, Stig R. T. Ekestorm:
A single-chip false target radar image generator for countering wideband imaging radars. 751-759 - Paul Leroux, Johan Janssens, Michiel Steyaert:
A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [for GPS receiver]. 760-765 - Kalle Kivekäs, Aarno Pärssinen, Jussi Ryynänen, Jarkko Jussila, Kari Halonen:
Calibration techniques of active BiCMOS mixers. 766-769 - Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez:
Transconductance amplifier structures with very small transconductances: a comparative design approach. 770-775 - Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez:
A CMOS transconductance amplifier architecture with wide tuning range for very low frequency applications. 776-781
Volume 37, Number 7, July 2002
- Christian C. Enz, Stefan Rusu:
Guest editorial. 795-797 - Teemu Salo, Saska Lindfors, Kari A. I. Halonen:
A 80-MHz bandpass ΔΣ modulator for a 100-MHz IF receiver. 798-808 - Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura:
A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching. 809-816 - Mustafa Keskin, Un-Ku Moon, Gabor C. Temes:
A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator using unity-gain-reset op amps. 817-824 - Marzia Annovazzi, Vittorio Colonna, Gabriele Gandolfi, Fabrizio Stefani, Andrea Baschirotto:
A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology. 825-834 - Bram De Muer, Michel S. J. Steyaert:
A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800. 835-844 - Peter R. Kinget, Robert C. Melville, David E. Long, Venugopal Gopinathan:
An injection-locking scheme for precision quadrature generation. 845-851 - Ryuichi Fujimoto, Kenji Kojima, Shoji Otaka:
A 7-GHz 1.8-dB NF CMOS low-noise amplifier. 852-856 - Hubert Weinberger, Andreas Wiesbauer, Christian Fleischhacker, Joerg Hauptmann, Thomas Ferianz, Michael Staber, Dietmar Sträußnigg, Berthold Seger:
An ADSL-RT full-rate analog front end IC with integrated line driver. 857-865 - Andreas Wiesbauer, Martin Clara, Moritz Harteneck, Thomas Pötscher, Berthold Seger, Christoph Sandner, Christian Fleischhacker:
A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS. 866-873 - Karl Schrödinger, Jaro Stimma, Manfred Mauthe:
A fully integrated CMOS receiver front-end for optic Gigabit Ethernet. 874-880 - Shinji Yamashita, Satoshi Ide, Kazuyuki Mori, Atsushi Hayakawa, Norio Ueno, Kazuhiro Tanaka:
Novel cell-AGC technique for burst-mode CMOS preamplifier with wide dynamic range and high sensitivity for ATM-PON system. 881-886 - Simona Brigati, Paolo Colombara, Lucio D'Ascoli, Umberto Gatti, Tibor Kerekes, Piero Malcovati:
A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON. 887-894 - Bahram Zand, David A. Johns:
High-speed CMOS analog Viterbi detector for 4-PAM partial-response signaling. 895-903 - Andreas Demosthenous, John Taylor:
A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder. 904-910 - Olaf Schrey, Jürgen Huppertz, Goran Filimonovic, Arndt Bußmann, Werner Brockherde, Bedrich J. Hosticka:
A 1 K×1 K high dynamic range CMOS image sensor with on-chip programmable region-of-interest readout. 911-915 - Michael Oberle, Robert Reutemann, Jürgen Hertle, Qiuting Huang:
A 10-mW two-channel fully integrated system-on-chip for eddy-current position sensing [in biomedical devices]. 916-925 - Yuyun Liao, David B. Roberts:
A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature. 926-931 - Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka:
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. 932-940 - Tobias Gemmeke, Michael Gansen, Tobias G. Noll:
Implementation of scalable power and area efficient high-throughput Viterbi decoders. 941-948 - Wolfgang Horn, Heinz Zitta:
A robust smart power bandgap reference circuit for use in an automotive environment. 949-952 - Judith Maget, Marc Tiebout, Rainer Kraus:
Influence of novel MOS varactors on the performance of a fully integrated UMTS VCO in standard 0.25-μm CMOS technology. 953-958