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ORCIDIEEE Journal of Solid-State Circuits, Volume 42
Volume 42, Number 1, January 2007
- James D. Warnock, William Bidermann, Albert van der Werf, Katsuyuki Sato:
Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference. 3-6 - Ana Sonia Leon, Kenway W. Tam, Jinuk Luke Shin, David Weisner, Francis Schumacher:
A Power-Efficient High-Throughput 32-Thread SPARC Processor. 7-16 - Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora:
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. 17-25 - Sapumal B. Wijeratne, Nanda Siddaiah, Sanu K. Mathew, Mark A. Anders, Ram K. Krishnamurthy, Jeremy Anderson, Matthew Ernest, Mark D. Nardin:
A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit. 26-37 - Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou:
Energy-Efficient GHz-Class Charge-Recovery Logic. 38-47 - Yolin Lih, Nestoras Tzartzanis, William W. Walker:
A Leakage Current Replica Keeper for Dynamic Circuits. 48-55 - Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin B. Cohen, Jamil A. Wakil:
Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements. 56-65 - Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner
, Saravanan Rajapandian, Tanay Karnik:
High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters. 66-73 - Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. 74-83 - Eugenio Cantatore, Thomas C. T. Geuns, Gerwin H. Gelinck, Erik van Veenendaal, Arnold F. A. Gruijthuijsen, Laurens Schrijnemakers, Steffen Drews, Dago M. De Leeuw:
A 13.56-MHz RFID System Based on Organic Transponders. 84-92 - Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai:
An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display. 93-100 - Hiroyuki Nakamoto, Daisuke Yamazaki, Takuji Yamamoto, Hajime Kurata, Satoshi Yamada, Kenji Mukaida, Tsuzumi Ninomiya, Takashi Ohkawa, Shoichi Masui, Kunihiko Gotoh:
A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology. 101-110 - Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. 111-122 - Reid R. Harrison, Paul T. Watkins, Ryan J. Kier, Robert O. Lovejoy, Daniel J. Black, Bradley Greger, Florian Solzbacher:
A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System. 123-133 - Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Andre Bonnardot, Steffen Buch, Matthias Sauer:
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions. 134-144 - Simon Damphousse, Khalid Ouici, Ahmed Rizki, A. Martin Mallinson:
All Digital Spread Spectrum Clock Generator for EMI Reduction. 145-150 - Davide De Caro, Nicola Petra, Antonio Giuseppe Maria Strollo:
A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 µm CMOS. 151-160 - Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Jiun-Yan Yang, Kang-Cheng Hou, Chen-Yi Lee:
A 125 µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications. 161-169 - Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang, Ming-Chih Tsai, Jiun-In Guo, Jinn-Shyan Wang:
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. 170-182 - Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu:
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. 183-192 - Kyu-Hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim:
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. 193-200 - Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura:
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. 201-209 - Sangbeom Kang, Woo Yeong Cho, Beak-Hyung Cho, KwangJin Lee, Changsoo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu-Hwan Ro, Suyeon Kim, Choong-Duk Ha, Ki-Sung Kim, Young-Ran Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim, YunSueng Shin:
A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation. 210-218 - Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima:
A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput. 219-232 - Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. 233-242
Volume 42, Number 2, February 2007
- Brian P. Ginsburg, Anantha P. Chandrakasan:
Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver. 247-257 - Ding-Lan Shen, Tai-Cheng Lee:
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers. 258-268 - Bharath Kumar Thandri, José Silva-Martínez:
A 63 dB SNR, 75-mW Bandpass RF ΣΔ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-µm SiGe BiCMOS Technology. 269-279 - Srinivasan Venkatesh, Guillermo J. Serrano, Jordan D. Gray, Paul E. Hasler:
A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation. 280-291 - Jianhong Xiao, Iuri Mehr, José Silva-Martínez:
A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner. 292-301 - Sam Mandegaran, Ali Hajimiri:
A Breakdown Voltage Multiplier for High Voltage Swing Drivers. 302-312 - Aleksandar Tasic, Su-Tarn Lim, Wouter A. Serdijn, John R. Long:
Design of Adaptive Multimode RF Front-End Circuits. 313-322 - Ahmed Amer, Emad Hegazi, Hani F. Ragaie:
A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation. 323-328 - Chih-Fan Liao, Shen-Iuan Liu:
A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers. 329-339 - Tsung-Hsien Lin, Yu-Jen Lai:
An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL. 340-349 - Antonio Giuseppe Maria Strollo, Davide De Caro, Nicola Petra:
A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique. 350-360 - Rong-Jyi Yang, Shen-Iuan Liu:
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm. 361-373 - Ali Fard, Pietro Andreani:
An Analysis of 1/f2 Phase Noise in Bipolar Colpitts Oscillators (With a Digression on Bipolar Differential-Pair LC Oscillators). 374-384 - Michael S. McCorquodale, Justin D. O'Day, Scott M. Pernia, Gordon A. Carichner, Sundus Kubba, Richard B. Brown:
A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0. 385-399 - Nathaniel J. Guilar, Frank Lau, Paul J. Hurst, Stephen H. Lewis:
A Passive Switched-Capacitor Finite-Impulse-Response Equalizer. 400-409 - Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda:
Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. 410-421 - Toshihiko Yamasaki, Tadashi Shibata:
A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection. 422-430 - Young-Ho Seo, Dong-Wook Kim:
VLSI Architecture of Line-Based Lifting Wavelet Transform for Motion JPEG2000. 431-440 - Urs Frey, Markus Graf, Stefano Taschini, Kay-Uwe Kirstein, Andreas Hierlemann:
A Digital CMOS Architecture for a Micro-Hotplate Array. 441-450 - Sanjeev Manandhar, Steven Eugene Turner, David E. Kotecki:
36-GHz, 16×6-Bit ROM in InP DHBT Technology Suitable for DDS Application. 451-456 - P. V. Ananda Mohan:
Comments on "A 4th-Order Active- Gm-RC Reconfigurable (UMTS/WLAN) Filter". 457-458 - Stefano D'Amico, Vito Giannini, Andrea Baschirotto:
Author's Reply. 458
Volume 42, Number 3, March 2007
- Sourja Ray, Bang-Sup Song:
A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching. 463-474 - Seung-Tak Ryu, Bang-Sup Song, Kantilal Bacrania:
A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse. 475-485 - Dongwon Seo, Gene H. McAllister:
A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter. 486-495 - Kong-Pang Pun, Shouri Chatterjee, Peter R. Kinget:
A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC. 496-507 - Juan M. Carrillo, Guido Torelli, Raquel Pérez-Aloe Valverde, J. Francisco Duque-Carrillo:
1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage. 508-517 - Marco Grassi, Piero Malcovati, Andrea Baschirotto:
A 160 dB Equivalent Dynamic Range Auto-Scaling Interface for Resistive Gas Sensors Arrays. 518-528 - Hakan Dogan, Robert G. Meyer:
Intermodulation Distortion in CMOS Attenuators and Switches. 529-539 - Arnoud P. van der Wel, Eric A. M. Klumperink, Jay S. Kolhatkar, Eric Hoekstra, Martijn F. Snoeij, Cora Salm, Hans Wallinga, Bram Nauta:
Low-Frequency Noise Phenomena in Switched MOSFETs. 540-550 - Patrick Reynaert, Michiel S. J. Steyaert:
A 2.45-GHz 0.13-µm CMOS PA With Parallel Amplification. 551-562 - Qiang Li, Y. P. Zhang:
CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency. 563-570 - Ankush Goel, Hossein Hashemi:
Frequency Switching in Dual-Resonance Oscillators. 571-582 - Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin Ilker Karsilayan:
A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz. 583-591 - Mahim Ranjan, Lawrence E. Larson:
A Low-Cost and Low-Power CMOS Receiver Front-End for MB-OFDM Ultra-Wideband Systems. 592-601 - Valentina Della Torre, Matteo Conta, Ramesh Chokkalingam, Giuseppe Cusmai, Paolo Rossi, Francesco Svelto:
A 20 mW 3.24mm2 Fully Integrated GPS Radio for Location Based Services. 602-612 - Niksa Tadic, Horst Zimmermann:
Low-Power BiCMOS Optical Receiver With Voltage-Controlled Transimpedance. 613-626 - Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda:
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. 627-636 - Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, Tatsuya Hirose:
A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology. 637-646 - Nicola Massari, Massimo Gottardi:
A 100 dB Dynamic-Range CMOS Vision Sensor With Programmable Image Processing and Global Feature Extraction. 647-657 - Sai Kit Lau, Philip K. T. Mok, Ka Nang Leung:
A Low-Dropout Regulator for SoC With Q-Reduction. 658-664 - H. Pooya Forghani-zadeh, Gabriel A. Rincón-Mora:
An Accurate, Continuous, and Lossless Self-Learning CMOS Current-Sensing Scheme for Inductor-Based DC-DC Converters. 665-679 - Benton H. Calhoun, Anantha P. Chandrakasan:
A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation. 680-688 - David Levacq, Vincent Dessard, Denis Flandre:
Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode. 689-702
Volume 42, Number 4, April 2007
- Krishnaswamy Nagaraj:
New Associate Editor. 719 - Stephen V. Kosonocky, Kazuo Yano:
Introduction to the Special Issue on the 2006 Symposium on VLSI Circuits. 720-721 - Shouri Chatterjee, Peter R. Kinget:
A 0.5-V 1-Msps Track-and-Hold Circuit With 60-dB SNDR. 722-729 - Patrick Y. Wu, Vincent Sin-Luen Cheung, Howard C. Luong:
A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture. 730-738 - Brian P. Ginsburg, Anantha P. Chandrakasan:
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC. 739-747 - Echere Iroaga, Boris Murmann:
A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling. 748-756 - Kazutaka Honda, Masanori Furuta, Shoji Kawahito:
A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques. 757-765 - Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji Kawahito:
A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters. 766-774 - Ting Wu, Kartikeya Mayaram, Un-Ku Moon:
An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators. 775-783 - Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno:
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution. 784-789 - Yuichi Hori, Tadahiro Kuroda:
A 0.79-mm2 29-mW Real-Time Face Detection Core. 790-797 - Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
CMOS Smart Sensor for Monitoring the Quality of Perishables. 798-803 - Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto:
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. 804-812 - Harold Pilo, Charlie Barwin, Geordie Braceras, Chris Browning, Steve Lamphier, Fred Towler:
An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage. 813-819 - Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. 820-829 - Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara:
MRAM Cell Technology for Over 500-MHz SoC. 830-838 - Stefan Dietrich, Michael Angerbauer, Milena Ivanov, Dietmar Gogl, Heinz Hoenigschmid, Michael Kund, Corvin Liaw, Michael Markert, Ralf Symanczyk, Laith Altimime, Serge Bournat, Gerhard Müller:
A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control. 839-845 - Jonathan Chang, Ming Huang, Jonathan Shoemaker, John Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, Raghuraman Ganesan, Gloria Leong, Venkata Lukka, Stefan Rusu, Durgesh Srivastava:
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. 846-852 - Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto:
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. 853-861 - Kunihiko Iizuka, Hiroshi Kawamura, Takanobu Fujiwara, Kanetomo Kagoshima, Shuichi Kawama, Hiroshi Kijima, Masato Koutani, Shinji Toyoyama, Keiichi Sakuno:
A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor. 862-871 - Afshin Momtaz, David Chung, Namik Kocaman, Jun Cao, Mario Caresosa, Bo Zhang, Ichiro Fujimori:
A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-µm CMOS. 872-880 - Jackie Koon Lun Wong, Alexander V. Rylyakov, Chih-Kong Ken Yang:
A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions. 881-888 - Azita Emami-Neyestanak, Aida Varzaghani, John F. Bulzacchelli, Alexander V. Rylyakov, Chih-Kong Ken Yang, Daniel J. Friedman:
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. 889-896 - Adrian Maxim, Ramin K. Poorfard, Richard A. Johnson, Philip John Crawley, James T. Kao, Zhiwei Dong, Madhu Chennam, Tim Nutt, David S. Trager, Mitchell Reid:
A Fully Integrated 0.13 µm CMOS Low-IF DBS Satellite Tuner Using Automatic Signal-Path Gain and Bandwidth Calibration. 897-921 - Dejan Markovic, Borivoje Nikolic, Robert W. Brodersen:
Power and Area Minimization for Multidimensional Signal Processing. 922-934 - Alberto Valdes-Garcia, Chinmaya Mishra, Faramarz Bahmani, José Silva-Martínez, Edgar Sánchez-Sinencio:
An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication. 935-948
Volume 42, Number 5, May 2007
- Krishnaswamy Nagaraj:
New Associate Editor. 951 - Derek K. Shaeffer:
Introduction to the Special Issue on the 2006 Radio Frequency Integrated Circuits (RFIC) Symposium. 952-953 - Asad A. Abidi:
The Path to the Software-Defined Radio Receiver. 954-966 - Adrian Maxim, Ramin K. Poorfard, Richard A. Johnson, Philip John Crawley, James T. Kao, Zhiwei Dong, Madhu Chennam, Tim Nutt, David S. Trager:
A Fully Integrated 0.13-µm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer. 967-982 - Tzung-Ming Chen, Yung-Ming Chiu, Chun-Cheng Wang, Ka-Un Chan, Ying-Hsi Lin, Ming-Chong Huang, Chao-Hua Lu, Wen-Shan Wang, Che-Sheng Hu, Chao-Cheng Lee, Jiun-Zen Huang, Bin-I Chang, Shih-Chieh Yen, Ying-Yao Lin:
A Low-Power Fullband 802.11a/b/g WLAN Transceiver With On-Chip PA. 983-991 - Khurram Muhammad, Thomas Murphy, Robert Bogdan Staszewski:
Verification of Digital RF Processors: RF, Analog, Baseband, and Software. 992-1002 - Denis C. Daly, Anantha P. Chandrakasan:
An Energy-Efficient OOK Transceiver for Wireless Sensor Networks. 1003-1011 - Taeksang Song, Hyoung-Seok Oh, Euisik Yoon, Songcheol Hong:
A Low-Power 2.4-GHz Current-Reused Receiver Front-End and Frequency Source for Wireless Sensor Network. 1012-1022 - Michael Reiha, John R. Long:
A 1.2 V Reactive-Feedback 3.1-10.6 GHz Low-Noise Amplifier in 0.13 µm CMOS. 1023-1033 - Saman Asgaran, M. Jamal Deen, Chih-Hung Chen, G. Ali Rezvani, Yasmin Kamali, Yukihiro Kiyota:
Analytical Determination of MOSFET's High-Frequency Noise Parameters From NF50 Measurements and Its Application in RFIC Design. 1034-1043 - Terry Yao, Michael Q. Gordon, Keith K. W. Tang, Kenneth H. K. Yau, Ming-Ta Yang, Peter Schvan, Sorin P. Voinigescu:
Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio. 1044-1057 - Swaminathan Sankaran, Kenneth K. O:
A Ultra-Wideband Amplitude Modulation (AM) Detector Using Schottky Barrier Diodes Fabricated in Foundry CMOS Technology. 1058-1064 - Theodoros Chalvatzis, Eric Gagnon, Morris Repeta, Sorin P. Voinigescu:
A Low-Noise 40-GS/s Continuous-Time Bandpass ΔΣ ADC Centered at 2 GHz for Direct Sampling Receivers. 1065-1075 - Paulo G. R. Silva, Lucien J. Breems, Kofi A. A. Makinwa, Raf Roovers, Johan H. Huijsing:
An IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range. 1076-1089 - Atsushi Yoshizawa, Yannis P. Tsividis:
A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation. 1090-1099 - Refet Firat Yazicioglu, Patrick Merken, Robert Puers, Chris Van Hoof:
A 60 µW 60 nV/√Hz Readout Front-End for Portable Biopotential Acquisition Systems. 1100-1110