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ORCIDIEEE Journal of Solid-State Circuits, Volume 29
Volume 29, Number 1, January 1994
- Yoshiki Tsujihashi, Hisashi Matsumoto, Hidekatsu Nishimaki, Atsushi Miyanishi, Hiroomi Nakao, Osamu Kitada, Shuhei Iwade, Shinpei Kayano, Masayoshi Sakao:
A high-density data-path generator with stretchable cells. 2-8 - Yohji Watanabe, Nobuo Nakamura, Shigeyoshi Watanabe:
Offset compensating bit-line sensing scheme for high density DRAM's. 9-13 - Graham A. Jullien, William C. Miller, Roger Grondin, Lino Del Pup, Sami S. Bizzan, David Zhang
:
Dynamic computational blocks for bit-level systolic arrays. 14-22 - Hans Hageraats, Pieter W. Hooijmans, Mark Tomesen:
A new wide-band input compensation for packaged analog and digital multigigabit IC's. 23-30 - Khaled M. Sharaf, Mohamed I. Elmasry:
An accurate analytical propagation delay model for high-speed CML bipolar circuits. 31-45 - Katsuji Kimura:
A bipolar four-quadrant analog quarter-square multiplier consisting of unbalanced emitter-coupled pairs and expansions of its input ranges. 46-55 - Jon S. Martens, Aleksandar Pance, Kookrin Char, Marie E. Johansson, Stephen R. Whiteley, Joel R. Wendt, Vincent M. Hietala, Tom A. Plut, Carol I. H. Ashby, Shang Y. Hou, Julia M. Phillips:
High-temperature superconducting shift registers operating at up to 100 GHz. 56-62 - Wen-Chung S. Wu, Ward J. Helms, Jay A. Kuhn, Bruce E. Byrkett:
Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges. 63-66 - Avner Efendovich, Yachin Afek, Coby Sella, Zeev Bikowsky:
Multifrequency zero-jitter delay-locked loop. 67-70 - Jeff Conger, Andrzej Peczalski, Michael S. Shur:
Modeling frequency dependence of GaAs MESFET characteristics. 71-76 - C. C. Lo, G. P. Li, J. H. Mulligan:
An approximation to the factor K in the Toh-Ko-Meyer MOS engineering model. 77-78
Volume 29, Number 2, February 1994
- Muhammad E. S. Elrabaa, Michael S. Obrecht, Mohamed I. Elmasry:
Novel low-voltage low-power full-swing BiCMOS circuits. 86-94 - K. Wayne Current:
Current-mode CMOS multiple-valued logic circuits. 95-107 - Cemal T. Dikmen, Numan S. Dogan, Mohamed A. Osman:
DC modeling and characterization of AlGaAs/GaAs heterojunction bipolar transistors for high-temperature applications. 108-116 - Alan Y. Kwentus, Hing-Tsun Hung, Alan N. Willson Jr.:
An architecture for high-performance/small-area multipliers for use in digital filtering applications. 117-121 - Bhavna Agrawal, Vivek K. De, Joseph M. Pimbley, James D. Meindl:
Short channel models and scaling limits of SOI and bulk MOSFETs. 122-125 - Attilio J. Rainal:
Eliminating inductive noise of external chip interconnections. 126-129 - Richard E. Vallee, Ezz I. El-Masr:
A very high-frequency CMOS complementary folded cascode amplifier. 130-133 - Thomas C. Banwell:
Simple precision bias circuit for medium-power amplifiers. 134-137 - Francesco Forti, Michael E. Wright:
Measurement of MOS current mismatch in the weak inversion region. 138-142 - Wim Van Petegem, Ben Geeraerts, Willy Sansen, Benny Graindourze:
Electrothermal simulation and design of integrated circuits. 143-146 - Massimo Lanzoni, Luciano Briozzo, Bruno Riccò:
A novel approach to controlled programming of tunnel-based floating-gate MOSFETs. 147-150 - N. Scheinberg, R. Michels:
A monolithic GaAs low power L-band successive detection logarithmic amplifier. 151-154 - Nils Hedenstiema, Kjell O. Jeppson:
Comments on the optimum CMOS tapered buffer problem. 155-158 - Laszlo Gal:
Reply to "Comments on the optimum CMOS tapered buffer problem". 158-159
Volume 29, Number 3, March 1994
- Yannis P. Tsividis:
Integrated continuous-time filter design - an overview. 166-176 - Rick A. Philpott, Robert A. Kertis, Ray Richetta, Timothy J. Schmerbeck, Donald J. Schulte:
A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection. 177-184 - Barry Thompson, Hae-Seung Lee, Lawrence M. DeVito:
A 300-MHz BiCMOS serial data transceiver. 185-192 - Louis A. Williams, Bruce A. Wooley:
A third-order sigma-delta modulator with extended dynamic range. 193-202 - Rajesh H. Zele, David J. Allstot:
Low-voltage fully differential switched-current filters. 203-209 - Yannis P. Tsividis, Ken Suyama:
MOSFET modeling for analog circuit CAD: problems and prospects. 210-216 - Richard J. Trihy, Ronald A. Rohrer:
A switched capacitor circuit simulator: AWEswit. 217-225 - Balsha R. Stanisic, Nishath K. Verghese, Rob A. Rutenbar, L. Richard Carley, David J. Allstot:
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis. 226-238 - Theodore L. Tewksbury, Hae-Seung Lee:
Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs. 239-252 - Khandker N. Quader, Eric R. Minami, Wei-Jen Huang, Ping K. Ko, Chenming Hu:
Hot-carrier-reliability design guidelines for CMOS logic circuits. 253-262 - Steven D. Millman, John M. Acken:
Special applications of the voting model for bridging faults. 263-270 - Dejan Mijuskovic, Martin Bayer, Thecla Chomicz, Nitin Garg, Frederick James, Philip McEntarfer, Jeff Porter:
Cell-based fully integrated CMOS frequency synthesizers. 271-279 - Tetsuro Kawata, Kenichi Kawauchi, Nobuaki Miyakawa, Ichiro Kawazome, Hiromi Yasumatsu, Susumu Haga, Masaya Takenaka:
An outline font rendering processor with an embedded RISC CPU for high-speed hint processing. 280-289 - Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada:
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. 290-297 - Fumio Murabayashi, Takashi Hotta, Shigeya Tanaka, Tatsumi Yamauchi, Hiromichi Yamada, Tetsuo Nakano, Yutaka Kobayashi, Tadaaki Bandoh:
3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. 298-302 - Reto Zimmermann, Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm. 303-307 - Kiyohiro Furutani, Hiroshi Miyamoto, Yoshikazu Morooka, M. Suwa, Hideyuki Ozaki:
An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM. 308-310 - Katsuhiko Ohsaki, Noriaki Asamoto, Shunichi Takagaki:
A single poly EEPROM cell structure for use in standard CMOS processes. 311-316 - Laurent Lemaitre, Marek J. Patyra, Daniel Mlynek:
Analysis and design of CMOS fuzzy logic controller in current mode. 317-322 - Norman J. Elias:
Acceptance sampling: an efficient, accurate method for estimating and optimizing parametric yield. 323-327 - Joongho Choi, Bing J. Sheu, Oscal T.-C. Chen:
A monolithic GaAs receiver for optical interconnect systems. 328-331 - Behzad Razavi, Yusuke Ota, Robert G. Swartz:
Design techniques for low-voltage high-speed digital bipolar circuits. 332-339 - C. Thomas Gray, Wentai Liu, Wilhelmus A. M. Van Noije, Thomas A. Hughes, Ralph K. Cavin III:
A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. 340-349 - Robert G. Meyer, William D. Mack:
A 1-GHz BiCMOS RF front-end IC. 350-355 - Samir S. Rofail, Mohamed I. Elmasry:
Schottky merged BiCMOS structures. 356-361 - Kalevi Hyyppä, Klas Ericson:
Low-noise photodiode-amplifier circuit. 362-365 - Joe Staudinger, Mike Golio, Charlie Woodin, Monica C. de Baca:
Considerations for improving the accuracy of large-signal GaAs MESFET models to predict power amplifier circuit performance. 366-373
Volume 29, Number 4, April 1994
- Bryan Ackland:
The role of VLSI in multimedia. 381-388 - Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura:
A 120-MHz BiCMOS superscalar RISC processor. 389-396 - John W. Fattaruso, Shivaling S. Mahant-Shetti, J. Brock Barton:
A fuzzy logic inference processor. 397-402 - Yasuo Unekawa, Tsuguo Kobayashi, Tsukasa Shirotori, Yukihiro Fujimoto, Takayoshi Shimazawa, Kazutaka Nogami, Takehiko Nakao, Kazukiro Sawada, Masataka Matsui, Takayasu Sakurai, Man Kit Tang, William A. Huffman:
A 110-MHz/1-Mb synchronous TagRAM. 403-410 - Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki:
A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. 411-418 - Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima:
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. 419-425 - Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe:
250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. 426-431 - Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima:
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. 432-440 - Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango:
Standby/active mode logic for sub-1-V operating ULSI memory. 441-447 - Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa:
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. 448-453 - Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara:
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. 454-460 - Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Hironori Banba, Kiyomi Naruke, Seiji Yamada, Yoichi Ohshima, Masamitsu Oshikiri, Yohei Hiura, Tomoko Yamane, Kuniyoshi Yoshikawa:
A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. 461-469 - Akira Matsuzawa:
Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment. 470-480 - Robert Adams, Tom Kwan:
A stereo asynchronous digital sample-rate converter for digital audio. 481-488 - Patrick Pai, Asad A. Abidi:
A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage read channels. 489-499 - Gunther M. Haller, Bruce A. Wooley:
A 700-MHz switched-capacitor analog waveform sampling circuit. 500-508 - Hae-Seung Lee:
A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC. 509-515 - Takahiro Miki, Hiroyuki Kouno, Toshio Kumamoto, Yasushi Kinoshita, Takayuki Igarashi, Keisuke Okada:
A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter. 516-522 - Hyun J. Shin:
A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits. 523-528 - Yunho Choi, Myungho Kim, Hyunsoon Jang, Taejin Kim, Seung-hoon Lee, Ho-cheol Lee, Churoo Park, Siyeol Lee, Cheol-soo Kim, Soo-In Cho, Ejaz Haq, J. Karp, Daeje Chin:
16-Mb synchronous DRAM with 125-Mbyte/s data rate. 529-533 - Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto, Hideyuki Ozaki:
An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs. 534-538 - Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi:
Open/folded bit-line arrangement for ultra-high-density DRAM's. 539-542
Volume 29, Number 5, May 1994
- Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi:
High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology. 546-550 - Wolfgang Pöhlmann:
A silicon-bipolar amplifier for 10 Gbit/s with 45 dB gain. 551-556 - Yusuke Ohtomo, Sadayuki Yasuda, Minoru Togashi, Massyuki Ino, Yasuyuki Tanabe, Jun-ichi Inoue, Masafumi Nogawa, Sshigeki Hino:
BiCMOS circuit technology for a 704 MHz ATM switch LSI. 557-563 - Tadahiro Kuroda, Yoshinori Sakata, Kenji Matsuo:
Analysis and optimization of BiCMOS gate circuits. 564-571 - Samir S. Rofail:
Low-voltage, low-power BiCMOS digital circuits. 572-579 - Jien-Chung Lo, Shih-Yao Sun, James C. Daly:
A concurrent error detection IC in 2-μm static CMOS logic. 580-584 - Long Yang, Steven D. Draving, Dan E. Mars, Mike R. T. Tan:
A 50 GHz broad-band monolithic GaAs/AlAs resonant tunneling diode trigger circuit. 585-595 - Victor Da Costa, Russel A. Martin:
Amorphous silicon shift register for addressing output drivers. 596-600 - Chong-Gun Yu, Randall L. Geiger:
An automatic offset compensation scheme with ping-pong control for CMOS operational amplifiers. 601-610 - M. J. McNutt, S. LeMarquis, J. L. Dunkley:
Systematic capacitance matching errors and corrective layout procedures. 611-616 - Oscar M. K. Law, C. André T. Salama:
GaAs split phase dynamic logic. 617-622 - Ming-Huei Shieh, Hung Chang Lin:
A multiple-dimensional multiple-state SRAM cell using resonant tunneling diodes. 623-630 - Rajendra Kumar:
NCMOS: a high performance CMOS logic. 631-633 - Dirk Timmermann, Bernold Rix, Helmut Hahn, Bedrich J. Hosticka:
A CMOS floating-point vector-arithmetic unit. 634-639 - P. T. Lai, Y. C. Cheng:
A closed-form delay expression for digital BiCMOS circuits with high-injection effects. 640-643
Volume 29, Number 6, June 1994
- Kjell O. Jeppson:
Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay. 646-654 - Patrik Larsson, Christer Svensson:
Noise in digital dynamic CMOS circuits. 655-662 - Dake Liu, Christer Svensson:
Power consumption estimation in CMOS VLSI chips. 663-670 - Mohamed Y. Osman, Mohamed I. Elmasry:
Highly testable design of BiCMOS logic circuits. 671-678 - Brian P. Brandt, Bruce A. Wooley:
A low-power, area-efficient digital filter for decimation and interpolation. 679-687 - Norman Scheinberg, R. Michels, V. Fedoroff, D. Stoffman, K. Li, S. Kent, M. Waight, D. Marz:
A GaAs up converter integrated circuit for a double conversion cable TV "set-top" tuner. 688-692 - Abdellatif Bellaouar, Issam S. Abu-Khater, Mohamed I. Elmasry, A. Chikima:
Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling. 693-700 - Robert G. Meyer, William D. Mack:
A wideband low-noise variable-gain BiCMOS transimpedance amplifier. 701-706 - Marc J. Loinaz, Bruce A. Wooley:
A BiCMOS time interval digitizer based on fully-differential, current-steering circuits. 707-714 - Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki:
A charge recycle refresh for Gb-scale DRAM's in file applications. 715-722 - Patrik Larsson, Christer Svensson:
Impact of clock slope on true single phase clocked (TSPC) CMOS circuits. 723-726 - Hai-Gang Yang, Steve Fluxman, Carlo Reita, Piero Migliorato:
Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers. 727-732 - Dima D. Shulman:
A static memory cell based on the negative resistance of the gate terminal of p-n-p-n devices. 733-736 - Nicholas C. Battersby, Chris Toumazou:
A high-frequency fifth order switched-current bilinear elliptic lowpass filter. 737-740 - Sherif H. K. Embabi, D. E. Brueske, K. Rachamreddy:
A BiCMOS low-power current mode gate. 741-745 - Navin Saxena, James J. Clark:
A four-quadrant CMOS analog multiplier for analog neural networks. 746-749 - Shen-Iuan Liu, Yuh-Shyan Hwang:
CMOS four-quadrant multiplier using bias feedback techniques. 750-752
Volume 29, Number 7, July 1994
- Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi:
Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit. 754-760 - Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Subthreshold-current reduction circuits for multi-gigabit DRAM's. 761-769 - Howard V. Savin, Mary S. Bucknell, Marc D. Spaulding, Thomas B. Maciukenas, W. Kent Fuchs:
Design for concurrent error detection and testability in storage/logic arrays. 770-779 - Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng:
New efficient designs for XOR and XNOR functions on the transistor level. 780-786 - Shayan Zhang, T. S. Kalkur, Steven Lee, Dengyuan Chen:
Analysis of the switching speed of BiCMOS buffer under high current. 787-796 - Shayan Zhang, T. S. Kalkur:
Analysis of BiCMOS buffer for input voltages with finite rise time. 797-807 - Norio Higashisaka, M. Shimada, Akira Ohta, Kenji Hosogi, Y. Tobita, Y. Mitsui:
GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's. 808-814 - Michael Möller, Hans-Martin Rein, Horst Wernz:
13 Gb/s Si-bipolar AGC amplifier IC with high gain and wide dynamic range for optical-fiber receivers. 815-822 - Badram Fotouhi:
Optimization of chopper amplifiers for speed and gain. 823-828 - Walter H. Henkels, Wei Hwang:
Large-signal 2T, 1C DRAM cell: signal and layout analysis. 829-832 - Bing Wang, James R. Hellums, Charles G. Sodini:
MOSFET thermal noise modeling for analog integrated circuits. 833-835 - C. T. Chuang, K. Chin:
High-speed low-power direct-coupled complementary push-pull ECL circuit. 836-839 - Pasqualino Visocchi, John T. Taylor, Richard Mason, Andrew Betts, David Haigh:
Design and evaluation of a high-precision, fully tunable OTA-C bandpass filter implemented in GaAs MESFET technology. 840-843