default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDA-SSCC 2014: KaoHsiung, Taiwan
- IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014. IEEE 2014, ISBN 978-1-4799-4090-5
- Hiroyuki Ohshima:
Mobile display technologies: Past, present and future. 1-4 - Alex Jinsung Choi:
Internet of Things: Evolution towards a hyper-connected society. 5-8 - Jongwoo Lee, Byungki Han, Jae-Hyun Lim, Su-Seob Ahn, Jae-Kwon Kim, Thomas Byunghak Cho:
A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregation. 9-12 - Makoto Oba, Eiji Okada, Ayako Tachibana, Koji Takahashi, Masahiko Sagisaka:
A low-power single-chip transceiver for 169/300/400/900 MHz band wireless sensor networks. 13-16 - Jun Deguchi, Toshiyuki Yamagishi, Hideaki Majima, Nau Ozaki, Kazuhiro Hiwada, Makoto Morimoto, Tatsuji Ashitani, Shouhei Kousai:
A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication. 17-20 - Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori, Shintaro Izumi, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability. 21-24 - Yoshisato Yokoyama, Yuichiro Ishii, Koji Tanaka, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi, Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba, Koji Nii:
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues. 25-28 - Kenta Yasufuku, Naoto Oshiyama, Toshitada Saito, Yukimasa Miyamoto, Yutaka Nakamura, Ryota Terauchi, Atsushi Kondo, Takuma Aoyama, Masafumi Takahashi, Yukihito Oowaki, Ryoichi Bandai:
A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput. 29-32 - Ting-Kuei Kuan, Yu-Hsuan Chiang, Shen-Iuan Liu:
A 0.43pJ/bit true random number generator. 33-36 - Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura:
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. 37-40 - Chao Wang, Jun Zhou, Xin Liu, Muthukumaraswamy Annamalai Arasu, Minkyu Je:
A sub-threshold to super-threshold Level Conversion Flip Flop for sub/near-threshold dual-supply operation. 41-44 - Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring. 45-48 - Hans Reyserhove, Nele Reynders, Wim Dehaene:
Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI. 49-52 - Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera:
A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation. 53-56 - Shih-Hsiung Chien, Ting-Hsuan Hung, Szu-Yu Huang, Tai-Haur Kuo:
A monolithic capacitor-current-controlled hysteretic buck converter with transient-optimized feedback circuit. 57-60 - Dong-Chul Park, Tae-Hwang Kong, Sukhwan Choi, Gyu-Hyeong Cho:
An 83% peak efficiency and 1.07W/mm2 power density Single Inductor 4-Output DC-DC converter with Bang-Bang Zeroth-Order Control. 61-64 - Yi-Ping Su, Chiun-He Lin, Te-Fu Yang, Ru-Yu Huang, Wei-Chung Chen, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee:
CCM/GM relative skip energy control in single-inductor multiple-output DC-DC converter for wearable device power solution. 65-68 - Pai-Yi Wang, Li-Te Wu, Tai-Haur Kuo:
A current-mode buck converter with bandwidth reconfigurable for enhanced efficiency and improved load transient response. 69-72 - Shang-Hsien Yang, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Jing-Jia Chen, Tsung-Yen Tsai, Chao-Cheng Lee:
A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interface. 73-76 - Chun-Cheng Liu:
A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS. 77-80 - Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen:
A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS. 81-84 - James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa:
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. 85-88 - Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici:
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS. 89-92 - Seonggeon Kim, Jaehyun Kang, Minjae Lee:
A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration. 93-96 - Shih-Hao Huang, Zheng-Hao Hong, Wei-Zen Chen:
A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. 97-100 - Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. 101-104 - Seong-Ho Lee, Duke Tran, Tamer A. Ali, Burak Çatli, Heng Zhang, Wei Zhang, Mohammed M. Abdul-Latif, Zhi Huang, Guansheng Li, Mahmoud Reza Ahmadi, Afshin Momtaz:
A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS. 105-108 - Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee:
Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology. 109-112 - Yu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, Bo Hu, Jun Zha, Steven Chuang:
A power management unit integrated ADSL/ADSL2+ CPE analog front-end with -93.5dB THD for DMT-based applications. 113-116 - Jack Yuan-Chen Sun:
Semiconductor innovation into the next decade. 117-120 - Vivek De:
Energy efficient computing in nanoscale CMOS: Challenges and opportunities. 121-124 - Hyunbae Lee, Taeksang Song, Sangyeon Byeon, Kwanghun Lee, Inhwa Jung, Seongjin Kang, Ohkyu Kwon, Koeun Cheon, Donghwan Seol, Jong-Ho Kang, Gunwoo Park, Yunsaing Kim:
A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel. 125-128 - Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang:
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. 129-132 - Wen-Pin Lin, Shyh-Shyuan Sheu, Chia-Chen Kuo, Pei-Ling Tseng, Meng-Fan Chang, Keng-Li Su, Chih-Sheng Lin, Kan-Hsueh Tsai, Sih-Han Lee, Szu-Chieh Liu, Yu-Sheng Chen, Heng-Yuan Lee, Ching-Chih Hsu, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao:
A nonvolatile look-up table using ReRAM for reconfigurable logic. 133-136 - Aravinthan Athmanathan, Milos Stanisavljevic, Junho Cheon, Seokjoon Kang, Changyong Ahn, Junghyuk Yoon, Min-Chul Shin, Taekseung Kim, Nikolaos Papandreou, Haris Pozidis, Evangelos Eleftheriou:
A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory. 137-140 - Anh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik-Joon Chang, Tony Tae-Hyoung Kim:
0.2 V 8T SRAM with improved bitline sensing using column-based data randomization. 141-144 - Ching-Wei Wu, Ming-Hung Chang, Chia-Cheng Chen, Robin Lee, Hung-Jen Liao, Jonathan Chang:
A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS. 145-148 - Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin:
A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C. 149-152 - Chih-Chan Tu, Feng-Wen Lee, Tsung-Hsien Lin:
An area-efficient capacitively-coupled instrumentation amplifier with a duty-cycled Gm-C DC servo loop in 0.18-μm CMOS. 153-156 - Sanghyun Heo, Hyunggun Ma, Jae Joon Kim, Franklin Bien:
Highly improved SNR differential sensing method using parallel operation signaling for touch screen application. 157-160 - Yat-Hei Lam, Seong-Jin Kim:
A 16.6μW 32.8MHz monolithic CMOS relaxation oscillator. 161-164 - Chin-Ho Chang, Jaw-Juinn Horng, Amit Kundu, Chih-Chiang Chang, Yung-Chow Peng:
An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET. 165-168 - Tzu-Chao Yan, Chun-Hsing Li, Chih-Wei Lai, Wei-Cheng Chen, Tzu-Yuan Chao, Chien-Nan Kuo:
CMOS THz transmissive imaging system. 169-172 - Kensuke Nakajima, Akihiro Maruyama, Masato Kohtani, Tsuyoshi Sugiura, Eiichiro Otobe, Jaejin Lee, Shinhee Cho, Kyusub Kwak, Jeongseok Lee, Toshihiko Yoshimasu, Minoru Fujishima:
23Gbps 9.4pJ/bit 80/100GHz band CMOS transceiver with on-board antenna for short-range communication. 173-176 - Dixian Zhao, Patrick Reynaert:
A 3 Gb/s 64-QAM E-band direct-conversion transmitter in 40-nm CMOS. 177-180 - Rui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs. 181-184 - Shita Guo, Tianzuo Xi, Ping Gui, Jing Zhang, Wooyeol Choi, Kenneth K. O, Yanli Fan, Daquan Huang, Richard Gu, Mark Morgan:
54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique. 185-188 - Seong-Jin Kim, Lei Liu, Lei Yao, Wang Ling Goh, Yuan Gao, Minkyu Je:
A 0.5-V sub-μW/channel neural recording IC with delta-modulation-based spike detection. 189-192 - Sunjoo Hong, Jaehyuk Lee, Joonsung Bae, Hoi-Jun Yoo:
A 10.4 mW electrical impedance tomography SoC for portable real-time lung ventilation monitoring system. 193-196 - Jian Xu, Tong Wu, Zhi Yang:
A power efficient frequency shaping neural recorder with automatic bandwidth adjustment. 197-200 - Lei Yao, Jianming Zhao, Peng Li, Rui-Feng Xue, Yong Ping Xu, Minkyu Je:
A 20V-compliance implantable neural stimulator IC with closed-loop power control, active charge balancing, and electrode impedance check. 201-204 - Alberto Rodríguez-Pérez, Manuel Delgado-Restituto, Angela A. Darie, Cristina Soto-Sánchez, Eduardo Fernández-Jover, Ángel Rodríguez-Vázquez:
A 330μW, 64-channel neural recording sensor with embedded spike feature extraction and auto-calibration. 205-208 - Injoon Hong, Gyeonghoon Kim, Youchang Kim, Donghyun Kim, Byeong-Gyu Nam, Hoi-Jun Yoo:
A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor. 209-212 - Youchang Kim, Gyeonghoon Kim, Injoon Hong, Donghyun Kim, Hoi-Jun Yoo:
A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems. 213-216 - Shin-ichi Yoshida, Mutsumi Hamaguchi, Takahiro Morishita, Shinji Shinjo, Akira Nagao, Masayuki Miyamoto:
An 87×49 mutual capacitance touch sensing IC enabling 0.5 mm-diameter stylus signal detection at 240 Hz-reporting-rate with palm rejection. 217-220 - Shin-Hao Chen, Shen-Yu Peng, Ke-Horng Chen, Shin-Chi Lai, Sheng Kang, Kevin Cheng, Ying-Hsi Lin, Chen-Chih Huang, Chao-Cheng Lee:
A 2.5W tablet speaker delivering 3.2W pseudo high power by psychoacoustic model based adaptive power management system. 221-224 - Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata:
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. 225-228 - Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee:
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. 229-232 - Jen-Huan Tsai, Sheng-An Ko, Hui-Huan Wang, Chia-Wei Wang, Hsin Chen, Po-Chiun Huang:
A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement. 233-236 - Yousr Ismail, Chih-Kong Ken Yang:
A 12-V charge pump-based square wave driver in 65-nm CMOS technology. 237-240 - Jaeyoung Choi, M. Kumarasamy Raja, M. Annamalai Arasu:
A programmable discrete-time filter employing hardware-efficient two-dimensional implementation method. 241-244 - Ye-Sing Luo, Shen-Iuan Liu:
A low-input-swing AC-DC voltage multiplier using Schottky diodes. 245-248 - Xinwang Zhang, Yang Xu, Bingqiao Liu, Qian Yu, Siyang Han, Qiongbing Liu, Zehong Zhang, Yanqiang Gao, Zhihua Wang, Baoyong Chi:
A 0.1-5GHz flexible SDR receiver in 65nm CMOS. 249-252 - Lei Wang, Yong Lian, Chun-Huat Heng:
A 1.44mm2 4-channel UWB beamforming receiver with Q-compensation in 65nm CMOS. 253-256 - Xiaobao Yu, Meng Wei, Yun Yin, Ying Song, Siyang Han, Qiongbing Liu, Zongming Jin, Xiliang Liu, Zhihua Wang, Baoyong Chi:
A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS. 257-260 - Yang Li, Ni Xu, Yining Zhang, Woogeun Rhee, Sanghoon Kang, Zhihua Wang:
A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications. 261-264 - Hiroyuki Ito, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, Noboru Ishihara, Kazuya Masu, Shoichi Masui, Youichi Momiyama:
An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI. 265-268 - Xiayun Liu, Teng Kok Hin, Chun-Huat Heng, Yuan Gao, Wei-Da Toh, San-Jeow Cheng, Minkyu Je:
A 103 pJ/bit multi-channel reconfigurable GMSK/PSK/16-QAM transmitter with band-shaping. 269-272 - Yuan-Fu Lin, Chang-Cheng Huang, Jiunn-Yih Max Lee, Chih-Tien Chang, Shen-Iuan Liu:
A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting. 273-276 - Zheng-Hao Hong, Wei-Zen Chen:
A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. 277-280 - Chien-Kai Kao, Kuan-Lin Fu, Shen-Iuan Liu:
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop. 281-284 - Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI. 285-288 - Li-Hung Chiueh, Tai-Cheng Lee:
A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit. 289-292 - Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee:
A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring. 293-296 - Hyunwoo Cho, Hyungwoo Lee, Joonsung Bae, Hoi-Jun Yoo:
A 5.2mW IEEE 802.15.6 HBC standard compatible transceiver with power efficient delay-locked-loop based BPSK demodulator. 297-300 - Wenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang:
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor. 301-304 - Chih-Chan Tu, Feng-Wen Lee, Dong-Feng Yeih, Tsung-Hsien Lin:
A 135-μW 0.46-mΩ/√Hz thoracic impedance variance monitor with square-wave current modulation. 305-308 - Jingren Gu, Huanfen Yao, Keping Wang, Babak A. Parviz, Brian P. Otis:
A 10μA on-chip electrochemical impedance spectroscopy system for wearables/implantables. 309-312 - Koichi Ishida, Reza Shabanpour, Bahman Kheradmand Boroujeni, Tilo Meister, Corrado Carta, Frank Ellinger, Luisa Petti, Niko Münzenrieder, Giovanni A. Salvatore, Gerhard Tröster:
22.5 dB open-loop gain, 31 kHz GBW pseudo-CMOS based operational amplifier with a-IGZO TFTs on a flexible film. 313-316 - Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu:
A 0.022mm2 98.5dB SNDR hybrid audio delta-sigma modulator with digital ELD compensation in 28nm CMOS. 317-320 - Yi Zhang, Chia-Hung Chen, Tao He, Xin Meng, Nancy Qian, Ed Liu, Phillip Elliott, Gabor C. Temes:
A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback. 321-324 - Cheng-En Hsieh, Shen-Iuan Liu:
A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS. 325-328 - Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin:
A 10b 100kS/s SAR ADC with charge recycling switching method. 329-332 - Harish Kundur Subramaniyan, Eric A. M. Klumperink, Bram Nauta, Venkatesh Srinivasan, Ali Kiaei:
RF transconductor linearization technique robust to process, voltage and temperature variations. 333-336 - Chin-Fu Li, Shih-Chieh Chou, Chang-Ming Lai, Cuei-Ling Hsieh, Jenny Yi-Chun Liu, Po-Chiun Huang:
A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer. 337-340 - Fei Song, Sam Chun-Geik Tan, Osama Shana'a:
An ultra-low-cost ESD-protected 0.65dB NF +10dBm OP1dB GNSS LNA in 0.18-μm SOI CMOS. 341-344 - Nai-Chung Kuo, Bonjern Yang, Chaoying Wu, Lingkai Kong, Angie Wang, Michael Reiha, Elad Alon, Ali M. Niknejad, Borivoje Nikolic:
A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers. 345-348 - Haoyu Qian, José Silva-Martínez:
A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOS. 349-352 - Xinwang Zhang, Zhihua Wang, Baoyong Chi:
A 0.1-1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration. 353-356 - Sang Gyun Kim, Seung-Hwan Jung, Yun Seong Eo, Seung-Hoon Kim, Xiao Ying, Hanbyul Choi, Chaerin Hong, Kyungmin Lee, Sung Min Park:
A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology. 357-360 - Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang:
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS. 361-364 - Sho Ikeda, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET. 365-368 - Zhao Zhang, Liyuan Liu, Nanjian Wu:
A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing. 369-372 - Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin:
Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. 373-376 - Jian Hong Jiang, Samir Parikh, Mark Lionbarger, Nikola Nedovic, Takuji Yamamoto:
A DC-46Gb/s 2: 1 multiplexer and source-series terminated driver in 20nm CMOS technology. 377-380 - Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara:
What is a good way to expand a silicon value to a solution value? 389-394
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-09 23:38 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
