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"A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a ..."

Rong-Jyi Yang, Shen-Iuan Liu (2005)

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DOI: 10.1093/IETELE/E88-C.8.1726

access: closed

type: Journal Article

metadata version: 2020-04-11

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Rong-Jyi Yang, Shen-Iuan Liu:
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector. IEICE Trans. Electron. 88-C(8): 1726-1730 (2005)

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