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ORCIDIEEE Journal of Solid-State Circuits, Volume 36
Volume 36, Number 1, January 2001
- Gopal Raghavan, Joseph F. Jensen, J. Laskowski, Michael Kardos, Michael G. Case, Marko Sokolich, Stephen Thomas III:
Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators. 5-13
- Vincent Sin-Luen Cheung, Howard Cam Luong
, Wing-Hung Ki:
A 1-V CMOS switched-opamp switched-capacitor pseudo-2-path filter. 14-22 - Thomas Hornak, Knud L. Knudsen, Andrew Z. Grzegorek, Ken A. Nishimura, William J. McFarland:
An image-rejecting mixer and vector filter with 55-dB image rejection over process, temperature, and transistor mismatch. 23-33 - Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka:
An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current. 34-39 - Albert Z. H. Wang, Chen-Hui Tsay:
An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology. 40-45 - Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara:
Design methodology of embedded DRAM with virtual-socket architecture. 46-54 - Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi:
Wordline voltage generating system for low-power low-voltage flash memories. 55-63 - Ralph Etienne-Cummings, Zaven Kevork Kalayjian, Donghui Cai:
A programmable focal-plane MIMD image processor chip. 64-73 - Peter H. Baechtold, Michael P. Beakes, Peter Buchmann, Rolf Clauberg, John F. Ewen, John F. Gilsdorf, Philippe Hauviller, Andreas Herkersdorf, Jean-Claude Le Garrec, Wolfram W. Lemppenau, Ben Parker, Dale J. Pearson, Joseph M. Pereira, Dominique Plassat, Scott K. Reynolds, Hans R. Schindler, André Steimle, David J. Webb, Albert X. Widmer:
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution. 74-80 - Josep Altet, Antonio Rubio, Emmanuel Schaub, Stefan Dilhaire, Wilfrid Claeys:
Thermal coupling in integrated circuits: application to thermal testing. 81-91 - Hui Tian, Boyd Fowler, Abbas El Gamal:
Analysis of temporal noise in CMOS photodiode active pixel sensor. 92-101 - Thierry Melly, Alain-Serge Porret, Christian C. Enz, Eric A. Vittoz:
An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers. 102-109 - Mike S. L. Lee, Bernard M. Tenbroek, William Redman-White, James Benson, Michael J. Uren:
A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation. 110-121 - Ming-Huang Liu, Shen-Iuan Liu:
An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique. 122-128 - Mikko Waltari, Kari A. I. Halonen:
1-V 9-bit pipelined switched-opamp ADC. 129-134 - Po-Chiun Huang, Yi-Huei Chen, Chorng-Kuang Wang:
A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier. 135-138 - Nikolay T. Tchamov, Tero Niemi, Niko Mikkola:
High-performance differential VCO based on Armstrong oscillator topology. 139-141 - Paavo Väänänen, Mikko Metsänvirta, Nikolay T. Tchamov:
A 4.3-GHz VCO with 2-GHz tuning range and low phase noise. 142-146 - Bahram Fotouhi:
All-MOS voltage-to-current converter. 147-151 - Hao-Ping Hong, Jiin-Chuan Wu:
A reverse-voltage protection circuit for MOSFET power switches. 152-155 - Michael Orshansky, Judy An, Chun Jiang, Bill Liu, Concetta Riccobene, Chenming Hu:
Efficient generation of pre-silicon MOS model parameters for early circuit design. 156-159 - Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider:
Addition to "Digitally programmable switched-current FIR filter for low-voltage applications". 160
Volume 36, Number 2, February 2001
- Ravi Gupta, Brian M. Ballweber, David J. Allstot:
Design and optimization of CMOS RF power amplifiers. 166-175 - Pieter Rombouts, Wim De Wilde, Ludo Weyten:
A 13.5-b 1.2-V micropower extended counting A/D converter. 176-183 - Myung-Jun Choe, Bang-Sup Song, Kantilal Bacrania:
An 8-b 100-MSample/s CMOS pipelined folding ADC. 184-194 - Andrea Boni, Andrea Pierazzi, Carlo Morandi:
A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS. 195-203 - William S. T. Yan, Howard C. Luong:
A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers. 204-216 - Kenneth S. Stevens, Shai Rotem, Ran Ginosar, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun, Rakefet Kol, Charles Dike, Marly Roncken:
An asynchronous instruction length decoder. 217-228 - Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee:
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. 229-238 - Yibin Ye, Kaushik Roy:
QSERL: quasi-static energy recovery logic. 239-248 - Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba:
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. 249-257 - Anders Edman, Jacob Christensen, Anders Emrich, Christer Svensson:
A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6-μm CMOS. 258-265 - Ching-Yuan Yang, Shen-Iuan Liu:
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques. 266-272 - Ganesh Balamurugan, Naresh R. Shanbhag:
The twin-transistor noise-tolerant dynamic circuit technique. 273-280 - Kimikazu Sano, Koichi Murata, Taiichi Otsuji, Tomoyuki Akeyoshi, Naofumi Shimizu, Eiichi Sano:
An 80-Gb/s optoelectronic delayed flip-flop IC using resonant tunneling diodes and uni-traveling-carrier photodiode. 281-289 - Ruchir Puri, Ching-Te Chuang, Mark B. Ketchen, Mario M. Pelella, Michael G. Rosenfield:
On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits. 290-298 - Dwight U. Thompson, Bruce A. Wooley:
A 15-b pipelined CMOS floating-point A/D converter. 299-303 - Chunyan Wang, M. Omair Ahmad, M. N. S. Swamy:
Design and implementation of a switched-current memory cell for low-power and weak-current operations. 304-307
Volume 36, Number 3, March 2001
- Lawrence E. Starr, Timothy T. Rueger:
Editorial. 312-314 - Anne Van den Bosch, Marc A. F. Borremans, Michel S. J. Steyaert, Willy Sansen:
A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. 315-324 - Jonathan C. Jensen, Lawrence E. Larson:
A broadband 10-GHz track-and-hold in Si/SiGe HBT technology. 325-330 - Robert C. Taft, Maria Rosaria Tursi:
A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V. 331-338 - Eric Fogleman, Jared Welz, Ian Galton:
An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC. 339-348 - Mohamed Dessouky, Andreas Kaiser:
Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping. 349-355 - Patrick P. Siniscalchi, Jeanne K. Pitz, Richard K. Hester, Stewart M. DeSoto, Minsheng Wang, Sucheendran Sridharan, Robert L. Halbach, Donald Richardson, William Bright, Maher M. Sarraj, James R. Hellums, Christopher L. Betty, Glenn H. Westphal:
A CMOS ADSL codec for central office applications. 356-365 - Tai-Cheng Lee, Behzad Razavi:
A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. 366-373 - Erich F. Haratsch, Kamran Azadet:
A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet. 374-384 - Kunihiko Iizuka, Masayuki Miyamoto, Yoshiji Ohta, Takahiro Suyama, Keita Hara, Shuichi Kawama, Hirofumi Matsui, Shin'ichiro Azuma, Shigenari Taguchi, Yoshihisa Fujimoto, Daniel Senderowicz:
CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops. 385-397 - Kyung-Ho Cho, Henry Samueli:
A frequency-agile single-chip QAM modulator with beamforming diversity. 398-407 - Robert Pasko, Luc Rijnders, Patrick R. Schaumont, Serge A. Vernalde, Daniela Duracková:
High-performance flexible all-digital quadrature up and down converter chip. 408-416 - David J. Foley, Michael P. Flynn:
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator. 417-423 - Tsung-Hsien Lin, William J. Kaiser:
A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop. 424-431 - Seema Butala Anand, Behzad Razavi:
A CMOS clock recovery circuit for 2.5-Gb/s NRZ data. 432-439 - Alexandre Vouilloz, Michel J. Declercq, Catherine Dehollain:
A low-power CMOS super-regenerative receiver at 1 GHz. 440-451 - Alain-Serge Porret, Thierry Melly, Dominique Python, Christian C. Enz, Eric A. Vittoz:
An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver. 452-466 - Thierry Melly, Alain-Serge Porret, Christian C. Enz, Eric A. Vittoz:
An ultralow-power UHF transceiver integrated in a standard digital CMOS process: transmitter. 467-472 - Min Xu, David K. Su, Derek K. Shaeffer, Thomas H. Lee, Bruce A. Wooley:
Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver. 473-485 - Feng-Jung Huang, Kenneth K. O:
A 0.5-μm CMOS T/R switch for 900-MHz wireless applications. 486-492 - Hui Wu, Ali Hajimiri:
Silicon-based distributed voltage-controlled oscillators. 493-502 - Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba:
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. 503-509 - Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi:
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. 510-515 - Michele Borgatti, Alessandro Rocchi, Marco Bisio, Monica Besana, Loris Navoni, Pier Luigi Rolandi:
A 64-min single-chip voice recorder/player using embedded 4-b/cell flash memory. 516-521 - Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Takemitsu Kunio:
NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors. 522-527 - Anne-Johan Annema, Govert J. G. M. Geelen, Peter C. de Jong:
5.5-V I/O in a 2.5-V 0.25-μm CMOS technology. 528-538 - Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata:
Physical design guides for substrate noise reduction in CMOS digital circuits. 539-549 - Mohamed W. Allam, Mohamed I. Elmasry:
Dynamic current mode logic (DyCML): a new low-power high-performance logic style. 550-558 - Patrick Rakers, Larry Connell, Tim Collins, Dan Russell:
Secure contactless smartcard ASIC with DPA protection. 559-565 - Chris Binan Wang:
A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme. 566-569 - Dorin Emil Calbaza, Yvon Savaria:
Direct digital frequency synthesis of low-jitter clocks. 570-572
Volume 36, Number 4, April 2001
- Takayuki Hamamoto, Kiyoharu Aizawa:
A computational image sensor with adaptive pixel-based integration time. 580-585 - Markus Loose, Karlheinz Meier, Johannes Schemmel:
A self-calibrating single-chip CMOS camera with logarithmic response. 586-596 - Jente B. Kuang, David H. Allen, Ching-Te Chuang:
Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology. 597-604 - Tae-Sik Cheung, Bhum-Cheol Lee, Eun-Chang Choi, Woo-Young Choi:
A 1.8∼3.2-GHz fully differential GaAs MESFET PLL. 605-610 - Alfio Zanchi, Carlo Samori, Salvatore Levantino, Andrea L. Lacaita:
A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop. 611-619 - Alireza Zolfaghari, Andrew Chan, Behzad Razavi:
Stacked inductors and transformers in CMOS technology. 620-628 - Paolo Cusinato, Davide Tonietto, Fabrizio Stefani, Andrea Baschirotto:
A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulator with 74-dB dynamic range. 629-638 - Nicolas Kauffmann, Sylvain Blayac, Miloud Abboun, Philippe André, Frédéric Aniel, Muriel Riet, Jean-Louis Benchimol, Jean Godin, Agnieszka Konczykowska:
InP HBT driver circuit optimization for high-speed ETDM transmission. 639-647 - Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam, Young Gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim:
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. 648-657 - Azeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl:
The impact of intrinsic device fluctuations on CMOS SRAM cell stability. 658-665 - Perng-Fei Lin, James B. Kuo:
A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell. 666-675 - Ming-Dou Ker, Tung-Yang Chen, Tai-Ho Wang, Chung-Yu Wu:
On-chip ESD protection design by using polysilicon diodes in CMOS process. 676-686 - Apisak Worapishet, John B. Hughes, Chris Toumazou:
Speed and accuracy enhancement techniques for high-performance switched-current comparators. 687-690 - Angus McLaren, Ken Martin:
Generation of accurate on-chip time constants and stable transconductances. 691-695 - Yasuhiro Sugimoto:
A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s. 696-700 - Ayman M. ElSayed, Mohamed I. Elmary:
Low-phase-noise LC quadrature VCO using coupled tank resonators in a ring structure. 701-705 - Andrea Boni, Andrea Pierazzi, Davide Vecchi:
LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS. 706-711 - S. C. Liu, F. A. Wu, James B. Kuo:
A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. 712-716
Volume 36, Number 5, May 2001
- Stephen H. Lewis:
New associate editor. 723 - David B. Scott, Masakazu Yamashina:
Guest editorial. 724-725 - Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda:
A bitline leakage compensation scheme for low-voltage SRAMs. 726-734 - Kyehyun Kyung, Hi-Choon Lee, Ki-Whan Song, Ho-Sung Song, Keewook Jung, Joon-Seo Moon, Byoung-Sul Kim, Sung-Burn Cho, Changhyun Kim, Soo-In Cho:
A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity. 735-743 - Ken Takeuchi, Tomoharu Tanaka:
A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories. 744-751 - Jared L. Zerbe, Pak Shing Chau, Carl W. Werner, Timothy P. Thrush, H. J. Liaw, Bruno W. Garlepp, Kevin S. Donnelly:
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus. 752-760 - Jafar Savoj, Behzad Razavi:
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. 761-768 - Helen H. Kim, S. Chandrasekhar, Charles A. Burrus, Jon Bauman:
A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver. 769-776 - Chan-Hong Park, Ook Kim, Beomsup Kim:
A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching. 777-783 - Yeon-Jae Jung, Seung-Wook Lee, Daeyun Shim, Wonchan Kim, Changhyun Kim, Soo-In Cho:
A dual-loop delay-locked loop using multiple voltage-controlled delay lines. 784-791 - Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie:
A clock distribution network for microprocessors. 792-799 - Kyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung-Wook Lee, Hyung Ki Huh, Deog-Kyoon Jeong, Wonchan Kim:
A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique. 800-809 - Behzad Razavi:
A 5.2-GHz CMOS receiver with 62-dB image rejection. 810-815 - Miguel E. Figueroa, David Hsu, Chris Diorio:
A mixed-signal approach to high-performance low-power linear filters. 816-822 - Changsik Yoo, Qiuting Huang:
A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-μm CMOS. 823-830 - Gerhard Knoblinger, Peter Klein, Marc Tiebout:
A new model for thermal channel noise of deep-submicron MOSFETs and its application in RF-CMOS design. 831-837 - Travis N. Blalock, Neela B. Gaddis, Ken A. Nishimura, Thomas A. Knotts:
True color 1024×768 microdisplay with analog in-pixel pulsewidth modulation and retinal averaging offset correction. 838-845 - Lisa G. McIlrath:
A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion. 846-853 - David S. Nack, Kenneth C. Dyer:
A constant slew rate Ethernet line driver. 854-858
Volume 36, Number 6, June 2001
- Ramesh Harjani:
A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process. 862-872 - Farbod Behbahani, Yoji Kishigami, John C. Leete, Asad A. Abidi:
CMOS mixers and polyphase filters for large image rejection. 873-887 - Osama Shana'a, Ivan Linscott, Len Tyler:
Frequency-scalable SiGe bipolar RF front-end design. 888-895 - Donhee Ham, Ali Hajimiri:
Concepts and methods in optimization of integrated LC VCOs. 896-909 - Lizhong Sun, Tadeusz Kwasniewski:
A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator. 910-916 - Jing-Ling Yang, Chiu-Sing Choy, Cheong-Fat Chan:
A self-timed divider using a new fast and robust pipeline scheme. 917-923 - Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. 924-932 - Ming-Luen Lieu, Tzi-Dar Chiueh:
A low-power digital matched filter for direct-sequence spread-spectrum signal acquisition. 933-943 - Yong-Ha Park, Seon-Ho Han, Jung-Hwan Lee, Hoi-Jun Yoo:
A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system. 944-955 - Hisatada Miyatake, Masahiro Tanaka, Yotaro Mori:
A design for high-speed low-power CMOS fully parallel content-addressable memory macros. 956-968