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ORCIDIEEE Journal of Solid-State Circuits, Volume 44
Volume 44, Number 1, January 2009
- Donhee Ham
, Hideto Hidaka, Ron Ho, Ram K. Krishnamurthy:
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. 3-6 - Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar:
Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor. 7-17 - Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer:
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor. 18-31 - Shidhartha Das, Carlos Tokunaga, Sanjay Pant, Wei-Hsiang Ma, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, David T. Blaauw:
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. 32-48 - Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. 49-63 - Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, John S. Liberty, Stephen Weitzel, John M. Keaty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman:
A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. 64-72 - Gianfranco Gerosa, Steve Curtis, Michael D'Addeo, Bo Jiang, Belliappa Kuttanna, Feroze Merchant, Binta Patel, Mohammed H. Taufique, Haytham Samarchi:
A Sub-2 W Low Power IA Processor for Mobile Internet Devices in 45 nm High-k Metal Gate CMOS. 73-82 - Masayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama:
A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU. 83-89 - Anders Nilsson, Eric Tell, Dake Liu:
An 11 mm2, 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12µm CMOS. 90-97 - Christian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang:
Design and Optimization of an HSDPA Turbo Decoder ASIC. 98-106 - Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar:
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. 107-114 - Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Anantha P. Chandrakasan:
A 65 nm Sub-Vt Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter. 115-126 - Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Liang-Gee Chen:
iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor. 127-135 - Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim, Hoi-Jun Yoo:
A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine. 136-147 - Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr:
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. 148-154 - Vinod Ramadurai, Harold Pilo, John Andersen, Geordie Braceras, John A. Gabric, Daniel Geise, Steve Lamphier, Yue Tan:
An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management. 155-162 - Naveen Verma, Anantha P. Chandrakasan:
A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing. 163-173 - Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi:
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. 174-185 - Raul Cernea, Long Pham, Farookh Moogat, Siu Lung Chan, Binh Le, Yan Li, Shouchang Tsao, Taiyuan Tseng, Khanh Nguyen, Jason Li, Jayson Hu, Jonghak Yuh, Cynthia Hsu, Fanglin Zhang, Teruhiko Kamei, Hiroaki Nasu, Phil Kliza, Khin Htoo, Jeffrey Lutze, Yingda Dong, Masaaki Higashitani, Junhui Yang, Hung-Szu Lin, Vamshi Sakhamuri, Alan Li, Feng Pan, Sridhar Yadala, Subodh Taigor, Kishan Pradhan, James Lan, Jim Chan, Takumi Abe, Yasuyuki Fukuda, Hideo Mukai, Koichi Kawakami, Connie Liang, Tommy Ip, Shu-Fen Chang, Jaggi Lakshmipathi, Sharon Huynh, Dimitris Pantelakis, Mehrdad Mofidi, Khandker Quader:
A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology. 186-194 - Yan Li, Seungpil Lee, Yupin Fong, Feng Pan, Tien-Chien Kuo, Jongmin Park, Tapan Samaddar, Hao Nguyen, Man Mui, Khin Htoo, Teruhiko Kamei, Masaaki Higashitani, Emilio Yero, Gyuwan Kwon, Phil Kliza, Jun Wan, Tetsuya Kaneko, Hiroshi Maejima, Hitoshi Shiga, Makoto Hamada, Norihiro Fujita, Kazunori Kanebako, Eugene Tam, Anne Koh, Iris Lu, Calvin Chia-Hong Kuo, Trung Pham, Jonathan Huynh, Qui Nguyen, Hardwell Chibvongodze, Mitsuyuki Watanabe, Ken Oowada, Grishma Shah, Byungki Woo, Ray Gao, Jim Chan, James Lan, Patrick Hong, Liping Peng, Debi Das, Dhritiman Ghosh, Vivek Kalluru, Sanjay Kulkarni, Raul-Adrian Cernea, Sharon Huynh, Dimitris Pantelakis, Chi-Ming Wang, Khandker Quader:
A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate. 195-207 - Ki-Tae Park, Myounggon Kang, Soonwook Hwang, Doo-Gon Kim, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-hoon Jang, Hansoo Kim, Yeong-Taek Lee, Soon-Moon Jung, Changhyun Kim:
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure. 208-216 - Ferdinando Bedeschi, Rich Fackenthal, Claudio Resta, Enzo Michele Donzè, Meenatchi Jagasivamani, Egidio Cassiodoro Buda, Fabio Pellizzer, David W. Chow, Alessandro Cabrini, Giacomo Matteo Angelo Calvi, Roberto Faravelli, Andrea Fantini, Guido Torelli, Duane Mills, Roberto Gastaldi, Giulio Casagrande:
A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage. 217-227 - David Ruffieux, Jérémie Chabloz, Matteo Contaldo, Claude Müller, Franz-Xaver Pengg, Paola Tortori, Alexandre Vouilloz, Patrick Volet, Christian C. Enz:
A Narrowband Multi-Channel 2.4 GHz MEMS-Based Transceiver. 228-239 - Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst:
A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters. 240-246 - Éric Colinet, Cedric Durand, Laurent Duraffourg, Patrick Audebert, Guillaume Dumas, Fabrice Casset, Eric Ollier, Pascal Ancey, Jean-François Carpentier, Lionel Buchaillot, Adrian M. Ionescu:
Ultra-Sensitive Capacitive Detection Based on SGMOSFET Compatible With Front-End CMOS Process. 247-257 - Jongmin Park, Taejoong Song, Joonhoi Hur, Sang Min Lee, Jungki Choi, Kihong Kim, Kyutae Lim, Chang-Ho Lee, Haksun Kim, Joy Laskar:
A Fully Integrated UHF-Band CMOS Receiver With Multi-Resolution Spectrum Sensing (MRSS) Functionality for IEEE 802.22 Cognitive Radio Applications. 258-268 - Nathan Pletcher, Simone Gambini, Jan M. Rabaey:
A 52 µW Wake-Up Receiver With -72 dBm Sensitivity Using an Uncertain-IF Architecture. 269-280 - Heinz-Gerd Graf, Christine Harendt, Thorsten Engelhardt, Cor Scherjon, Karsten Warkentin, Harald Richter, Joachim N. Burghartz:
High Dynamic Range CMOS Imager Technologies for Biomedical Applications. 281-289 - Albrecht Rothermel, Liu Liu, Naser Pour Aryan, Michael Fischer, Juergen Wuenschmann, Steffen Kibbel, Alex Harscher:
A CMOS Chip With Active Pixel Array and Specific Test Features for Subretinal Implantation. 290-300 - Clint L. Schow, Fuad E. Doany, Chen Chen, Alexander V. Rylyakov, Christian W. Baks, Daniel M. Kuchta, Richard A. John, Jeffrey A. Kash:
Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link. 301-313
Volume 44, Number 2, February 2009
- Bram Nauta:
New Associate Editor. 319 - Heng Zhang, Xiaohua Fan, Edgar Sánchez-Sinencio:
A Low-Power, Linearized, Ultra-Wideband LNA Design Technique. 320-330 - Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems. 331-343 - Jonathan Borremans, Steven Thijs, Piet Wambacq, Yves Rolain, Dimitri Linten, Maarten Kuijk:
A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5-6 GHz CMOS LNA. 344-353 - Raymond E. Barnett, Jin Liu, Steve Lazar:
A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders. 354-370 - Kenneth A. Townsend, James W. Haslett:
A Wideband Power Detection System Optimized for the UWB Spectrum. 371-381 - Nobuo Sasaki, Kentaro Kimoto, Wataru Moriyama, Takamaro Kikkawa:
A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection. 382-393 - Vishal V. Kulkarni, Muhammad Muqsith, Kiichi Niitsu, Hiroki Ishikuro, Tadahiro Kuroda:
A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna. 394-403 - Jennifer N. Kitchen, Connie Chu, Sayfe Kiaei, Bertan Bakkaloglu:
Combined Linear and Δ-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters. 404-413 - Hui Zheng, Shuzuo Lou, Dongtian Lu, Cheng Shen, Tatfu Chan, Howard C. Luong:
A 3.1 GHz-8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-µm CMOS Process. 414-426 - Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. 427-435 - Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Peter Buchmann, Christian Menolfi, Thomas Toifl, Martin L. Schmatz:
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. 436-449 - ChuanKang Liang, Behzad Razavi:
Systematic Transistor and Inductor Modeling for Millimeter-Wave Design. 450-457 - Youngcheol Chae, Gunhee Han:
Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator. 458-472 - Martin Anderson, Lars Sundström:
Design and Measurement of a CT ΔΣ ADC With Switched-Capacitor Switched-Resistor Feedback. 473-483 - Josep Rius, Maurice Meijer:
Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors. 484-494 - Hesam Amir Aslanzadeh, Erik John Pankratz, Edgar Sánchez-Sinencio:
A 1-V +31 dBm IIP3, Reconfigurable, Continuously Tunable, Power-Adjustable Active-RC LPF. 495-508 - Chang-Seok Chae, Hanh-Phuc Le, Kwang-Chan Lee, Gyu-Ha Cho, Gyu-Hyeong Cho:
A Single-Inductor Step-Up DC-DC Switching Converter With Bipolar Outputs for Active Matrix OLED Mobile Display Panels. 509-524 - Chih-Wen Lu:
A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for LCD Drivers. 525-537 - Armin Tajalli, Yusuf Leblebici:
A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. 538-548 - Sotirios Zogopoulos, Won Namgoong:
High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding. 549-557 - Zheng Xu, Kenneth L. Shepard:
Design and Analysis of Actively-Deskewed Resonant Clock Networks. 558-568 - Radu Zlatanovici, Sean Kao, Borivoje Nikolic:
Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example. 569-583 - Xiongfei Meng, Resve A. Saleh:
An Improved Active Decoupling Capacitor for "Hot-Spot" Supply Noise Reduction in ASIC Designs. 584-593 - Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga:
HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis. 594-608 - Mohammad Sharifkhani, Manoj Sachdev:
SRAM Cell Stability: A Dynamic Perspective. 609-619 - Mohammad Sharifkhani, Manoj Sachdev:
An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS. 620-630 - Stanley Schuster, Richard E. Matick:
Fast Low Power eDRAM Hierarchical Differential Sense Amplifier. 631-641 - Ya-Chun Lai, Shi-Yu Huang:
Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT). 642-649 - Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. 650-658 - Taeg Sang Cho, Kyeong-Jae Lee, Jing Kong, Anantha P. Chandrakasan:
A 32-µW 1.83-kS/s Carbon Nanotube Chemical Sensor System. 659-669
Volume 44, Number 3, March 2009
- Tae Wook Kim, Harish Muthali, Susanta Sengupta, Kenneth Barnett, James Jaffee:
Multi-Standard Mobile Broadcast Receiver LNA With Integrated Selectivity and Novel Wideband Impedance Matching Technique. 675-685 - Donggu Im, Ilku Nam, Hong-Teuk Kim, Kwyro Lee:
A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner. 686-698 - Osama Shana'a:
A 2.4-2.5 GHz WLAN Direct-Conversion Receiver Front-End With Low-Distortion Baseband Filters. 699-707 - Namjun Cho, Long Yan, Joonsung Bae, Hoi-Jun Yoo:
A 60 kb/s-10 Mb/s Adaptive Frequency Hopping Transceiver for Interference-Resilient Body Channel Communication. 708-717 - Daniel L. Kaczman, Manish Shah, Mohammed Alam, Mohammed Rachedine, David L. Cashen, Lu M. Han, Anand Raghavan:
A Single-Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and +90 dBm IIP2. 718-739 - Ming-Ching Kuo, Shiau-Wen Kao, Chih-Hung Chen, Tsung-Shuen Hung, Yi-Shing Shih, Tzu-Yi Yang, Chien-Nan Kuo:
A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 µm CMOS. 740-750 - Ali Parsa, Behzad Razavi:
A New Transceiver Architecture for the 60-GHz Band. 751-762 - Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa:
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. 763-774 - Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, Shen-Iuan Liu:
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology. 775-783 - Ibrahim R. Chamas, Sanjay Raman:
Analysis and Design of a CMOS Phase-Tunable Injection-Coupled LC Quadrature VCO (PTIC-QVCO). 784-796 - Li-min Lee, Chih-Kong Ken Yang:
An LC-Based Clock Buffer With Tunable Injection Locking. 797-807 - Yunliang Zhu, Jonathan D. Zuegel, John R. Marciante, Hui Wu:
Distributed Waveform Generator: A New Circuit Technique for Ultra-Wideband Pulse Generation, Shaping and Modulation. 808-823 - Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. 824-834 - Sami Kurtti, Juha Kostamovaara:
Laser Radar Receiver Channel With Timing Detector Based on Front End Unipolar-to-Bipolar Pulse Shaping. 835-847 - Hüseyin Dinc, Phillip E. Allen:
A 1.2 GSample/s Double-Switching CMOS THA With -62 dB THD. 848-861 - Zhiheng Cao, Shouli Yan, Yunchu Li:
A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 µm CMOS. 862-873 - Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. 874-882 - Byung-Geun Lee, Robin M. Tsang:
A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-gm Opamp. 883-890 - Song-Bok Kim, Stefan Joeres, Ralf Wunderlich, Stefan Heinen:
A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 µm CMOS. 891-900 - Aida Varzaghani, Chih-Kong Ken Yang:
A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization. 901-915 - Kyehyung Lee, Qingdong Meng, Tetsuro Sugimoto, Koichi Hamashita, Kaoru Takasuka, Seiji Takeuchi, Un-Ku Moon, Gabor C. Temes:
A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver. 916-927 - Ronan A. R. van der Zee, Fred Mostert:
Output Impedance Shaping for Frequency Compensation of MOS Audio Power Amplifiers. 928-934 - Giby Samson, Lawrence T. Clark:
Low-Power Race-Free Programmable Logic Arrays. 935-946 - Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A High-Speed Inductive-Coupling Link With Burst Transmission. 947-955 - Chang-Tzu Wang, Ming-Dou Ker:
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology. 956-964 - Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Yue Tan:
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. 965-976 - Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara:
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. 977-986 - Meng-Fan Chang, Shin-Jang Shen:
A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme. 987-994 - Joseph N. Y. Aziz, Karim Abdelhalim, Ruslana Shulyzki, Roman Genov, Berj L. Bardakjian, Miron Derchansky, Demitre Serletis, Peter L. Carlen:
256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes. 995-1005 - Andreas G. Katsiamis, Emmanuel M. Drakakis, Richard F. Lyon:
A Biomimetic, 4.5µW, 120+ dB, Log-Domain Cochlea Channel With AGC. 1006-1022
Volume 44, Number 4, April 2009
- Katsu Nakamura, Masayuki Mizuno:
Introduction to the Special Issue on the 2008 Symposium on VLSI Circuits. 1039-1040 - Chun-Ying Chen, Michael Q. Le, Kwang Young Kim:
A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration. 1041-1046 - Hans Van de Vel, Berry A. J. Buter, Hendrik van der Ploeg, Maarten Vertregt, Govert J. G. M. Geelen, Edward J. F. Paulus:
A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS. 1047-1056 - Jason Hu, Noam Dolev, Boris Murmann:
A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification. 1057-1066 - Xiaodan Zou, Xiaoyuan Xu, Libin Yao, Yong Lian:
A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip. 1067-1077 - Hyunsik Park, Ki Young Nam, David K. Su, Katelijn Vleugels, Bruce A. Wooley:
A 0.7-V 870-µW Digital-Audio CMOS Sigma-Delta Modulator. 1078-1088 - Matthew Z. Straayer, Michael H. Perrott:
A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping. 1089-1098 - Ming-Hsin Huang, Ke-Horng Chen:
Single-Inductor Multi-Output (SIMO) DC-DC Converters With High Light-Load Efficiency and Minimized Cross-Regulation for Portable Devices. 1099-1111 - Feng Su, Wing-Hung Ki, Chi-Ying Tsui:
Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation. 1112-1120 - Nasser A. Kurd, Praveen Mosalikanti, Mark Neidengard, Jonathan Douglas, Rajesh Kumar:
Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking. 1121-1129 - Dean Nguyen Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen, Christine Watnik, Anh Thien Tran, Zhibin Xiao, Eric W. Work, Jeremy W. Webb, Paul Vincent Mejia, Bevan M. Baas:
A 167-Processor Computational Platform in 65 nm CMOS. 1130-1144 - Scott Hanson, Mingoo Seok, Yu-Shiang Lin, Zhiyoong Foo, Daeyeon Kim, Yoonmyung Lee, Nurrachman Liu, Dennis Sylvester, David T. Blaauw:
A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode. 1145-1155 - Yu-Shiang Lin, Dennis Sylvester, David T. Blaauw:
Alignment-Independent Chip-to-Chip Communication for Sensor Applications Using Passive Capacitive Signaling. 1156-1166 - Edith Beigné, Fabien Clermidy, Hélène Lhermet, Sylvain Miermont, Yvain Thonnart, Xuan-Tu Tran, Alexandre Valentian, Didier Varreau, Pascal Vivet, Xavier Popon, Hugo Lebreton:
An Asynchronous Power Aware and Adaptive NoC Based Circuit. 1167-1177 - Kenichi Kawasaki, Tetsuyoshi Shiota, Koichi Nakayama, Atsuki Inoue:
A Sub-µs Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support. 1178-1183 - Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Koji Hosogi, Hiroaki Nakata, Masakazu Ehama, Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe:
A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS. 1184-1191 - Keiichi Kushida, Azuma Suzuki, Gou Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, Takahiko Sasaki, Akira Katayama, Yuki Fujimura, Tomoaki Yabe:
A 0.7 V Single-Supply SRAM With 0.495 µm2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme. 1192-1198 - Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De:
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. 1199-1208