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ORCIDIEEE Journal of Solid-State Circuits, Volume 40
Volume 40, Number 1, January 2005
- Georgios K. Konstadinidis, Anantha P. Chandrakasan, Sreedhar Natarajan, Thucydides Xanthopoulos:
Introduction to the Special Issue on the ISSCC2004. 3-6 - Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Howard Levy, Ha Pham, Jinseung Son, Nathan Moon, Dina Bistry, Umesh Nair, Mandeep Singh, Vikas Mathur, Ana Sonia Leon:
A dual-core 64-bit ultraSPARC microprocessor for dense server applications. 7-18 - Norman J. Rohrer, Cédric Lichtenau, Peter A. Sandon, Paul Kartschoke, Erwin B. Cohen, Miles G. Canada, Thomas Pflüger, Mathew I. Ringler, Rolf B. Hilgendorf, Stephen F. Geissler, Jeffrey S. Zimmerman:
A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features. 19-27 - Masakatsu Nakai, Satoshi Akui, Katsunori Seno, Tetsumasa Meguro, Takahiro Seki, Tetsuo Kondo, Akihiko Hashiguchi, Hirokazu Kawahara, Kazuo Kumano, Masayuki Shimura:
Dynamic voltage and frequency management for a low-power embedded microprocessor. 28-35 - Daniel J. Deleganes, Micah Barany, George L. Geannopoulos, Kurt Kreitzer, Matthew Morrise, Dan Milliron, Anant P. Singh, Sapumal B. Wijeratne:
Low-voltage swing logic circuits for a Pentium® 4 processor integer core. 36-43 - Sanu K. Mathew, Mark A. Anders, Brad Bloechel, Trang Nguyen, Ram K. Krishnamurthy, Shekhar Borkar:
A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS. 44-51 - Hugh McIntyre, Dennis Wendell, K. James Lin, P. Kaushik, Suresh Seshadri, Alfred Wang, V. Sundararaman, Ping Wang, Song Kim, Wen-Jay Hsu, Hee-Choul Park, Gideon Levinsky, Jiejun Lu, M. Chirania, Raymond A. Heald, Paul Lazar, Sanjaya Dharmasena:
A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor. 52-59 - Masaya Sumita, Shiro Sakiyama, Masayoshi Kinoshita, Yuta Araki, Yuichiro Ikeda, Kohei Fukuoka:
Mixed body bias techniques with fixed Vt and Ids generation circuits. 60-66 - Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi:
An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs. 67-79 - James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan Casper, Aaron Martin, Joseph T. Kennedy, Naresh R. Shanbhag, Randy Mooney:
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew. 80-88 - Jin-Hyun Kim, Sua Kim, Woo-Seop Kim, Jung-Hwan Choi, Hong-Sun Hwang, Changhyun Kim, Suki Kim:
A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling. 89-101 - Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle:
Uniform-phase uniform-amplitude resonant-load global clock distributions. 102-109 - (Withdrawn) Notice of Violation of IEEE Publication Principles: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation. 110-131
- Anne-Johan Annema
, Bram Nauta, Ronald van Langevelde, Hans Tuinhout:
Analog circuits in ultra-deep-submicron CMOS. 132-143 - Chinh H. Doan, Sohrab Emami, Ali M. Niknejad, Robert W. Brodersen:
Millimeter-wave CMOS design. 144-155 - Brian A. Floyd, Scott K. Reynolds, Ullrich R. Pfeiffer, Thomas Zwick, Troy J. Beukema, Brian P. Gaucher:
SiGe bipolar transceiver circuits operating at 60 GHz. 156-167 - Shunichi Kaeriyama, Toshitsugu Sakamoto, Hiroshi Sunamura, Masayuki Mizuno, Hisao Kawaura, Tsuyoshi Hasegawa, Kazuya Terabe, Tomonobu Nakayama, Masakazu Aono:
A nonvolatile programmable solid-electrolyte nanometer switch. 168-176 - Hiroshi Kawaguchi, Takao Someya, Tsuyoshi Sekitani, Takayasu Sakurai:
Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin. 177-185 - Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada:
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. 186-194 - Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni:
A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. 195-203 - Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. 204-212 - John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva:
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. 213-222 - Sang-Bo Lee, Seong-Jin Jang, Jin-Seok Kwak, Sang-Jun Hwang, Young-Hyun Jun, Soo-In Cho, Chil-Gee Lee:
A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. 223-232 - Joseph T. Kennedy, Randy Mooney, Robert Ellis, James E. Jaussi, Shekhar Borkar, Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Steffen Loeffler, Jochen Hoffmann, Wolfgang Hokenmaier, Russ Houghton, Thomas Vogelsang:
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. 233-244 - Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. 245-253 - Sungdae Choi, Kyomin Sohn, Hoi-Jun Yoo:
A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture. 254-260 - Ken Mai, Ron Ho, Elad Alon, Dean Liu, Younggon Kim, Dinesh Patil, Mark A. Horowitz:
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS. 261-275 - Shigeru Nakahara, Takahiro Kawata:
A design for a minimum Hamming-distance search using asynchronous digital techniques. 276-285 - Kunisato Yamaoka, Shunichi Iwanari, Yasuo Murakuki, Hiroshige Hirano, Masahiko Sakagami, Tetsuji Nakakuma, Takashi Miki, Yasushi Gohou:
A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure. 286-292 - Woo Yeong Cho, Beak-Hyung Cho, Byung-Gil Choi, Hyung-Rok Oh, Sangbeom Kang, Ki-Sung Kim, Kyung-Hee Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Youngnam Hwang, SuJin Ahn, Gwan-Hyeob Koh, Gitae Jeong, Hongsik Jeong, Kinam Kim:
A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM). 293-300 - Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian, Bradley J. Garni, Halbert S. Lin, Asim Omair, William L. Martino:
A 4-Mb 0.18-μm 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers. 301-309 - Alice Wang, Anantha P. Chandrakasan:
A 180-mV subthreshold FFT processor using a minimum energy design methodology. 310-319 - David Garrett, Graeme K. Woodward, Linda M. Davis, Chris Nicol:
A 28.8 Mb/s 4 × 4 MIMO 3G CDMA receiver for frequency selective channels. 320-330 - Hideki Yamauchi, Shigeyuki Okada, Kazuhiko Taketa, Yuh Matsuda, Tsugio Mori, Tsuyoshi Watanabe, Yoshihiro Matsuo, Yoshifumi Matsushita:
1440 × 1080 pixel, 30 frames per second motion-JPEG 2000 codec for HD-movie transmission. 331-341 - Goang Seog Choi, Joo Seon Kim, Hyun Jeong Park, Young Jun Ahn, Hyun Soo Park, Jum Han Bae, In Sik Park, Dong Ho Shin:
A 0.18-μm CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML. 342-350
Volume 40, Number 2, February 2005
- Krishnaswamy Nagaraj:
New Associate Editor. 359 - Albert C. Jerng, Charles G. Sodini:
The impact of device type and sizing on phase noise mechanisms. 360-369 - Burcin Baytekin, Robert G. Meyer:
Analysis and simulation of spectral regrowth in radio frequency power amplifiers. 370-381 - Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Mayaram, Terri S. Fiez:
Simulation and measurement of supply and substrate noise in mixed-signal ICs. 382-391 - Ilku Nam, Kwyro Lee:
High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology. 392-402 - Yann Le Guillou, Olivier Gaborieau, Patrice Gamand, Martin Isberg, Peter Jakobsson, Lars Jonsson, David Le Déaut, Hervé Marie, Sven Mattisson, Laurent Monge, Torbjörn Olsson, Sébastien Prouet, Tobias Tired:
Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time ΣΔ ADC. 403-411 - Andreas Demosthenous, Iasonas F. Triantis:
An adaptive ENG amplifier for tripolar cuff electrodes. 412-421 - Arun Rao, William McIntyre, Un-Ku Moon, Gábor C. Temes:
Noise-shaping techniques applied to switched-capacitor voltage regulators. 422-429 - Julius Georgiou, Christopher Toumazou:
A 126-μW cochlear chip for a totally implantable system. 430-443 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A 375 × 365 high-speed 3-D range-finding image sensor using row-parallel search architecture and multisampling technique. 444-453 - Michiel A. P. Pertijs, Andrea Niederkorn, Xu Ma, Bill McKillop, Anton Bakker, Johan H. Huijsing:
A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.5°C from -50°C to 120°C. 454-461 - Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. Conroy, Beomsup Kim:
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer. 462-471 - Mingdeng Chen, Jose Silva-Martinez, Michael Nix, Moises E. Robinson:
Low-voltage low-power LVDS drivers. 472-479 - Woopyo Jeong, Kaushik Roy:
High-performance low-power dual transition preferentially sized (DTPS) logic. 480-484 - Steven J. E. Wilton, Noha Kafafi, James C. H. Wu, Kimberly A. Bozman, Victor O. Aken'Ova, Resve Saleh:
Design considerations for soft embedded programmable logic cores. 485-497 - Lawrence T. Clark, Franco Ricci, Manish Biyani:
Low standby power state storage for sub-130-nm technologies. 498-506 - Antonino Conte, Gianbattista Lo Giudice, Gaetano Palumbo, Alfredo Signorello:
A high-performance very low-voltage current sense amplifier for nonvolatile memories. 507-514 - Chiu-Chiao Chung, Hongchin Lin, Yen-Tai Lin:
A novel high-speed sense amplifier for Bi-NOR flash memories. 515-522 - Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara:
Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories. 523-531 - Xicheng Jiang, Mau-Chung Frank Chang:
A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging. 532-535 - Maziar Tavakoli, Rahul Sarpeshkar:
A sinh resistor and its application to tanh linearization. 536-543 - Chang-Wan Kim, Min-Suk Kang, Phan Tuan Anh, Hoon-Tae Kim, Sang-Gug Lee:
An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system. 544-547 - Chia-Hsin Wu, Chih-Hun Lee, Wei-Sheng Chen, Shen-Iuan Liu:
CMOS wideband amplifiers using multiple inductive-series peaking technique. 548-552 - Frank Ellinger:
60-GHz SOI CMOS traveling-wave amplifier with NF below 3.8 dB from 0.1 to 40 GHz. 553-558 - Jri Lee, Behzad Razavi:
Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology". 559 - Sudhakar Pamarti, Lars C. Jansson, Ian Galton:
Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation". 559
Volume 40, Number 3, March 2005
- Krishnaswamy Nagaraj:
New Associate Editor. 575 - Bert Serneels, Tim Piessens, Michiel Steyaert, Wim Dehaene:
A high-voltage output driver in a 2.5-V 0.25-μm CMOS technology. 576-583 - Xiaohua Fan, Chinmaya Mishra, Edgar Sánchez-Sinencio:
Single Miller capacitor frequency compensation technique for low-power multistage amplifiers. 584-592 - Xiaofeng Lin, Sooping Saw, Jin Liu:
A CMOS 0.25-μm continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission. 593-602 - Todd S. Kaplan, Joseph F. Jensen, Charles H. Fields, Mau-Chung Frank Chang:
A 2-GS/s 3-bit ΔΣ-modulated DAC with tunable bandpass mismatch shaping. 603-610 - Angelo Scuderi, Luca La Paglia, Antonino Scuderi, Francesco Carrara, Giuseppe Palmisano:
A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control. 611-621 - Karim W. Hamed, Alois P. Freundorfer, Yahia M. M. Antar:
A monolithic double-balanced direct conversion mixer with an integrated wideband passive balun. 622-629 - Reza Navid, Thomas H. Lee, Robert W. Dutton:
Minimum achievable phase noise of RC oscillators. 630-637 - William F. Andress, Donhee Ham:
Standing wave oscillators utilizing wave-adaptive tapered transmission lines. 638-651 - KaChun Kwok, Howard C. Luong:
Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback. 652-660 - Hsiang-Hui Chang, Shen-Iuan Liu:
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop. 661-670 - Ken Yamamoto, Minoru Fujishima:
A 44-μW 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range. 671-677 - John W. M. Rogers, Foster F. Dai, Mark S. Cavin, David G. Rahn:
A multiband ΔΣ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC. 678-689 - Paolo Rossi, Antonio Liscidini, Massimo Brandolini, Francesco Svelto:
A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications. 690-697 - Hooman Darabi, Janice Chiu, Shahla Khorram, Hea Joung Kim, Zhimin Zhou, Hung-Ming (Ed) Chien, Brima Ibrahim, E. Geronaga, Long H. Tran, Ahmadreza Rofougaran:
A dual-mode 802.11b/bluetooth radio in 0.35-μm CMOS. 698-706 - Spyros Pipilos, Yannis Papananos, Nikolaos Naskas, Manolis Zervakis, Jakob Jongsma, Tony Gschier, Nigel Wilson, Jo Gibbins, Bob Carter, Graham Dann:
A transmitter IC for TETRA systems based on a Cartesian feedback loop linearization technique. 707-718 - Makoto Takamiya, Masayuki Mizuno:
A 6.7-fF/μm2 bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL. 719-725 - Kwangseok Han, Joonho Gil, Seong-Sik Song, Jeonghu Han, Hyungcheol Shin, Choong-Ki Kim, Kwyro Lee:
Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier. 726-735 - Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama, Hubert Siedhoff:
A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator. 736-743 - Ehsan Afshari, Ali Hajimiri:
Nonlinear transmission lines for pulse shaping in silicon. 744-752 - Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, Sergio Benedetto:
A 0.35-μm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code. 753-762 - Mohanasankar Sivaprakasam, Wentai Liu, Mark S. Humayun, James D. Weiland:
A variable range bi-phasic current stimulus driver circuitry for an implantable retinal prosthetic device. 763-771 - Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui:
A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation. 772-780 - Kenneth W. H. Ng, Vincent S. L. Cheung, Howard C. Luong:
A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques. 781-784 - Kenneth W. H. Ng, Vincent S. L. Cheung, Howard C. Luong:
A 28-MHz wideband switched-capacitor bandpass filter with transmission zeros for high attenuation. 785-790 - Toru Masuda, Kenichi Ohhata, Nobuhiro Shiramizu, Eiji Ohue, Katsuya Oda, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Takashi Harada, Katsuyoshi Washio:
SiGe-HBT-based 54-gb/s 4: 1 multiplexer IC with full-rate clock for serial communication systems. 791-795 - Jong K. Kim, Thottam S. Kalkur:
High-speed current-mode logic amplifier using positive feedback and feed-forward source-follower techniques for high-speed CMOS I/O buffer. 796-802 - Jose Alfredo Tirado-Mendez, Hildeberto Jardón-Aguilar:
Comments on "On unilateral dual feedback low-noise amplifier with simultaneous noise, impedance, and IIP3 Match". 803
Volume 40, Number 4, April 2005
- Bruce Gieseke, Tadahiro Kuroda:
Introduction to the Special Issue. 811-812 - Makoto Nagata, Takeshi Okumoto, Kazuo Taki:
A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits. 813-819 - Elad Alon, Vladimir Stojanovic, Mark A. Horowitz:
Circuits and techniques for high-resolution measurement of on-chip power supply noise. 820-828 - Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda:
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. 829-837 - Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar:
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. 838-845 - Saravanan Rajapandian, Zheng Xu, Kenneth L. Shepard:
Implicit DC-DC downconversion through charge-recycling. 846-852 - Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara:
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. 853-861 - Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi:
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. 862-869 - Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh:
A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. 870-876 - Myoung-Kyu Seo, Soung-Hoon Sim, Myoung-Hee Oh, Hyo-Sang Lee, Sang-Won Kim, In-Wook Cho, Gyu-Hong Kim, Moon-Gone Kim:
A 130-nm 0.9-V 66-MHz 8-Mb (256K × 32) local SONOS embedded flash EEPROM. 877-883 - Wing K. Luk, Robert H. Dennard:
A novel dynamic memory cell with internal voltage gain. 884-894 - Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr:
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. 895-901 - Dietmar Gogl, Christian Arndt, John C. Barwin, Alexander Bette, John K. DeBrosse, Earl T. Gow, Heinz Hoenigschmid, Stefan Lammers, Mark C. Lamorey, Yu Lu, Tom Maffitt, Kim Maloney, Werner Obermaier, Andre Sturm, Hans Viehmann, Dennis R. Willmott, Mark A. Wood, William J. Gallagher, Gerhard Mueller, Arkalgud R. Sitaram:
A 16-Mb MRAM featuring bootstrapped write drivers. 902-908 - Axel D. Berny, Ali M. Niknejad, Robert G. Meyer:
A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration. 909-917 - Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators. 918-925 - Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata:
A low-power and compact CDMA matched filter based on switched-current technology. 926-932 - Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar:
Area-efficient linear regulator with ultra-fast load regulation. 933-940 - Shiro Dosho, Naoshi Yanagisawa, Akira Matsuzawa:
A background optimization method for PLL by measuring phase jitter performance. 941-950 - Diego Barrettino, Sadik Hafizovic, Tormod Volden, Jan Sedivý, Kay-Uwe Kirstein, Andreas Hierlemann:
CMOS monolithic mechatronic microsystem for surface imaging and force response studies. 951-959 - Jipeng Li, Gil-Cho Ahn, Dong-Young Chang, Un-Ku Moon:
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR. 960-969 - Mario Valla, Giampiero Montagna, Rinaldo Castello, Riccardo Tonietto, Ivan Bietti:
A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner. 970-977 - Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura:
A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization. 978-985 - Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda:
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. 986-993 - Timothy O. Dickson, Rudy Beerkens, Sorin P. Voinigescu:
A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic. 994-1003 - Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, Mark A. Horowitz:
A 20-Gb/s 0.13-μm CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer. 1004-1011 - Vladimir Stojanovic, Andrew Ho, Bruno W. Garlepp, Fred Chen, Jason Wei, Grace Tsang, Elad Alon, Ravi T. Kollipara, Carl W. Werner, Jared L. Zerbe, Mark A. Horowitz:
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. 1012-1026 - Kazuko Nishimura, Hiroshi Kimura, Manabu Watanabe, Tetsuya Nagai, Kazuhiro Nojima, Kazumasa Gomyo, Masato Takata, Mitsuhiro Iwamoto, Hiroaki Asano:
A 1.25-Gb/s CMOS burst-mode optical transceiver for ethernet PON system. 1027-1034
Volume 40, Number 5, May 2005
- Carl R. Grace, Paul J. Hurst, Stephen H. Lewis:
A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration. 1038-1046 - Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu:
A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. 1047-1056 - Sotirios Limotyrakis, Scott D. Kulchycki, David K. Su, Bruce A. Wooley:
A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC. 1057-1067 - Antonio J. López-Martín, Sushmita Baswa, Jaime Ramírez-Angulo, Ramón González Carvajal:
Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency. 1068-1077 - Antonio J. López-Martín, Jaime Ramírez-Angulo, Chandrika Durbha, Ramón González Carvajal:
A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion. 1078-1083 - Sining Zhou, Mau-Chung Frank Chang:
A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver. 1084-1093 - Eunseok Song, Yido Koo, Yeon-Jae Jung, Deok-Hee Lee, Sangyoung Chu, Soo-Ik Chae:
A 0.25-μm CMOS quad-band GSM RF transceiver using an efficient LO frequency plan. 1094-1106 - Pietro Andreani, Xiaoyan Wang, Luca Vandi, Ali Fard:
A study of phase noise in colpitts and LC-tank CMOS oscillators. 1107-1118 - Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Hong-June Park:
A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme. 1119-1129 - Sung-Rung Han, Shen-Iuan Liu:
A single-path pulsewidth control loop with a built-in delay-locked loop. 1130-1135 - Hoi Lee, Philip K. T. Mok:
Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler. 1136-1146 - Masaki Sakakibara, Shoji Kawahito, Dwi Handoko, Nobuo Nakamura, Hiroki Satoh, Mizuho Higashi, Keiji Mabuchi, Hirofumi Sumi:
A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers. 1147-1156 - Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen:
Design techniques for single-low-VDD CMOS systems. 1157-1165 - Thomas E. Collins, Vikas Manan, Stephen I. Long:
Design analysis and circuit enhancements for high-speed bipolar flip-flops. 1166-1174 - Yongsam Moon, Sang-Hyun Lee, Daeyun Shim:
A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS. 1175-1179 - Peter Ossieur, Dieter Verhulst, Yves Martens, Wei Chen, Johan Bauwelinck, Xing-Zhi Qiu, Jan Vandewege:
A 1.25-gb/s burst-mode receiver for GPON applications. 1180-1189 - Jonathan R. Haigh, Michael W. Wilkerson, Jay B. Miller, Timothy S. Beatty, Stephen J. Strazdus, Lawrence T. Clark:
A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. 1190-1199 - Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi:
A 400-MHz random-cycle dual-port interleaved DRAM (D2RAM) with standard CMOS Process. 1200-1207
Volume 40, Number 6, June 2005
- Krishnaswamy Nagaraj:
New Associate Editor. 1211 - Peter R. Kinget:
Device mismatch and tradeoffs in the design of analog circuits. 1212-1224 - Alfio Zanchi, Frank (Ching-Yuh) Tsay:
A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter. 1225-1237 - Ramón González Carvajal, Jaime Ramírez-Angulo, Gladys Omayra Ducoudray, Antonio J. López-Martín:
High-speed high-precision CMOS analog rank order filter with O(n) complexity. 1238-1248 - Chun-Pang Wu, Hen-Wai Tsao:
A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function. 1249-1258 - Vojkan Vidojkovic, Johan van der Tang, Arjan J. Leeuwenburgh, Arthur H. M. van Roermund:
A low-voltage folded-switching mixer in 0.18-μm CMOS. 1259-1264 - Darius Jakonis, Kalle Folkesson, Jerzy J. Dabrowski, Patrik Eriksson, Christer Svensson:
A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS. 1265-1277 - Tino Copani, Santo A. Smerzi, Giovanni Girlando, Giuseppe Palmisano:
A 12-GHz silicon bipolar dual-conversion receiver for digital satellite applications. 1278-1287 - Kazuya Yamamoto:
A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique. 1288-1295 - Zhenbiao Li, Kenneth K. O:
A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator. 1296-1302 - Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi:
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture. 1303-1309 - Byung-Guk Kim, Lee-Sup Kim:
A 250-MHz-2-GHz wide-range delay-locked loop. 1310-1321 - Johan Bauwelinck, Wei Chen, Dieter Verhulst, Yves Martens, Peter Ossieur, Xing-Zhi Qiu, Jan Vandewege:
A high-resolution burst-mode laser transmitter with fast and accurate level monitoring for 1.25 Gb/s upstream GPONs. 1322-1330 - Jongsun Kim, Ingrid Verbauwhede, Mau-Chung Frank Chang:
A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus. 1331-1340 - Pasi Palojärvi, Tarmo Ruotsalainen, Juha Kostamovaara:
A 250-MHz BiCMOS receiver channel with leading edge timing discriminator for a pulsed time-of-flight laser rangefinder. 1341-1349 - Leif Lindgren, Johan Melander, Robert Johansson, Björn Möller:
A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging. 1350-1359 - Chua-Chin Wang, Jian-Ming Huang, Hon-Chen Cheng, Ron Hu:
Switched-current 3-bit CMOS 4.0-MHz wideband random signal generator. 1360-1365 - Byung-Do Yang, Lee-Sup Kim:
A low-power SRAM using hierarchical bit line and local sense amplifiers. 1366-1376 - Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer:
An 800-MHz embedded DRAM with a concurrent refresh mode. 1377-1387 - Wei-Zen Chen, Ying-Lien Cheng, Da-Shin Lin:
A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end. 1388-1396 - Derek K. Shaeffer, Thomas H. Lee:
Corrections to "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier". 1397-1398
Volume 40, Number 7, July 2005
- Rolf Koch, Stefan Rusu:
Introduction to the Special Issue on ESSCIRC'2004. 1403-1405 - Johannes Sturm, Martin Leifhelm, Harald Schatzmayr, Stefan Groiß, Horst Zimmermann:
Optical receiver IC for CD/DVD/blue-laser application. 1406-1413 - Jinho Ko, Jongmoon Kim, Sanghyun Cho, Kwyro Lee:
A 19-mW 2.6-mm2 L1/L2 dual-band CMOS GPS receiver. 1414-1425 - Jere A. M. Järvinen, Jouni Kaukovuori, Jussi Ryynänen, Jarkko Jussila, Kalle Kivekäs, Mauri Honkanen, Kari A. I. Halonen:
2.4-GHz receiver for sensor applications. 1426-1433 - Dimitri Linten, Steven Thijs, Mahadeva Iyer Natarajan, Piet Wambacq, Wutthinan Jeamsaksiri, Javier Ramos, Abdelkarim Mercha, Snezana Jenei, Stéphane Donnay, Stefaan Decoutere:
A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS. 1434-1442 - David Chamla, Andreas Kaiser, Andreia Cathelin, Didier Belot:
A Gm-C low-pass filter for zero-IF mobile applications with a very wide tuning range. 1443-1450 - Alessandro Italia, Luca La Paglia, Antonino Scuderi, Francesco Carrara, Egidio Ragonese, Giuseppe Palmisano:
A silicon bipolar transmitter front-end for 802.11a and HIPERLAN2 wireless LANs. 1451-1459 - Manuel Delgado-Restituto, Antonio J. Acosta, Ángel Rodríguez-Vázquez:
A mixed-signal integrated circuit for FM-DCSK modulation. 1460-1471 - Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Maarten Kuijk:
Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates. 1472-1481 - Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi:
A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS. 1482-1490 - Vittorio Colonna, Marzia Annovazzi, Gianluigi Boarin, Gabriele Gandolfi, Fabrizio Stefani, Andrea Baschirotto:
A 0.22-mm2 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dB SNRout. 1491-1498 - Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner:
A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS. 1499-1505 - Terje Nortvedt Andersen, Bjørnar Hernes, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Øystein Moldsvor:
A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS. 1506-1513 - Xiaohong Peng, Willy Sansen:
Transconductance with capacitances feedback compensation for multistage amplifiers. 1514-1520 - Robert Swoboda, Johannes Knorr, Horst Zimmermann:
A 5-Gb/s OEIC with voltage-up-converter. 1521-1526 - Sotir Ouzounov, Engel Roza, Johannes A. (Hans) Hegt, Gerard van der Weide, Arthur H. M. van Roermund:
A CMOS V-I converter with 75-dB SFDR and 360-μW power consumption. 1527-1532 - Mario Motz, Dieter Draxelmayr, Tobias Werth, Bernhard Forster:
A chopped Hall sensor with small jitter and programmable "True Power-on" function. 1533-1540 - Jan F. J. Wouters, Jan Sevenhans, Stefaan Van Hoogenbemt, Thierry Fernandez, Jeff Biggs, Carl Das, Steven A. M. Dupont:
A novel active feedback flyback with only 100-mV inductive overshoot for a standard low-voltage CMOS inductive load driver, in a single-chip controller for 73 relays in a POTS/ADSL splitter application. 1541-1548 - Klaus von Arnim, Eduardo Borinski, Peter Seegebrecht, Horst Fiedler, Ralf Brederlow, Roland Thewes, Jörg Berthold, Christian Pacha:
Efficiency of body biasing in 90-nm CMOS for low-power digital circuits. 1549-1556 - Ferdinando Bedeschi, Roberto Bez, Chiara Boffino, Edoardo Bonizzoni, Egidio Cassiodoro Buda, Giulio Casagrande, Lucio Costa, Marco Ferraro, Roberto Gastaldi, Osama Khouri, Federica Ottogalli, Fabio Pellizzer, Agostino Pirovano, Claudio Resta, Guido Torelli, Marina Tosi:
4-Mb MOSFET-selected μtrench phase-change memory experimental chip. 1557-1565 - Andreas Burg, Moritz Borgmann, Markus Wenk, Martin Zellweger, Wolfgang Fichtner, Helmut Bölcskei:
VLSI implementation of MIMO detection using the sphere decoding algorithm. 1566-1577 - Makoto Ogawa, Tadashi Shibata:
A delay-encoding-logic array processor for dynamic-programming matching of data sequences. 1578-1582 - Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki:
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. 1583-1588
Volume 40, Number 8, August 2005
- Heemin Y. Yang, Rahul Sarpeshkar:
A time-based energy-efficient analog-to-digital converter. 1590-1601 - Vladimir P. Petkov, Bernhard E. Boser:
A fourth-order ΣΔ interface for micromachined inertial sensors. 1602-1609 - David Hernandez-Garduno, Jose Silva-Martinez:
Continuous-time common-mode feedback for high-speed switched-capacitor networks. 1610-1617 - Xin He, William B. Kuhn:
A 2.5-GHz low-power, high dynamic range, self-tuned Q-enhanced LC filter in SOI. 1618-1628 - David G. Rahn, Mark S. Cavin, Fa Foster Dai, Neric H. W. Fong, Richard Griffith, José Macedo, A. David Moore, John W. M. Rogers, Mike Toner:
A fully integrated multiband MIMO WLAN transceiver RFIC. 1629-1641 - Poki Chen, Chun-Chi Chen, Chin-Chung Tsai, Wen-Fu Lu:
A time-to-digital-converter-based CMOS smart temperature sensor. 1642-1648 - Carlos Galup-Montoro, Márcio C. Schneider, Hamilton Klimach, Alfredo Arnaud:
A compact model of MOSFET mismatch for circuit design. 1649-1657 - Ullas Singh, Michael M. Green:
High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz. 1658-1661 - Ram Singh Rana:
Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-μm CMOS technology. 1662-1670 - Geum-Young Tak, Seok-Bong Hyun, Tae Young Kang, Byoung Gun Choi, Seong Su Park:
A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications. 1671-1679 - Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda:
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. 1680-1687 - Jae-Yoon Sim, Won Namgoong:
Multilevel differential encoding with precentering for high-speed parallel link transceiver. 1688-1694 - Hitoyuki Tagami, Tatsuya Kobayashi, Yoshikuni Miyata, Kazuhide Ouchi, Kazushige Sawada, Kazuo Kubo, Katsuhiko Kuno, Hideo Yoshida, Katsuhiro Shimizu, Takashi Mizuochi, Kuniaki Motoshima:
A 3-bit soft-decision IC for powerful forward error correction in 10-Gb/s optical communication systems. 1695-1705 - Sasa Radovanovic, Anne-Johan Annema, Bram Nauta:
A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication. 1706-1717 - Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer:
A 285-MHz pipelined MAP decoder in 0.18-μm CMOS. 1718-1725 - Yu-Wei Lin, Hsuan-Yu Liu, Chen-Yi Lee:
A 1-GS/s FFT/IFFT processor for UWB applications. 1726-1735 - Byung-Do Yang, Lee-Sup Kim:
A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver. 1736-1744 - Seung-Min Jung, Jin-Moon Nam, Dong-Hoon Yang, Moon-Key Lee:
A CMOS integrated capacitive fingerprint sensor with 32-bit RISC microcontroller. 1745-1750 - Ming-Dou Ker, Kun-Hsien Lin:
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs. 1751-1759
Volume 40, Number 9, September 2005
- Albert Z. H. Wang, Sreedhar Natarajan, Jafar Savoj:
Introduction to the Special Issue on the IEEE 2004 Custom Integrated Circuits Conference. 1775-1777 - Benton H. Calhoun, Alice Wang, Anantha P. Chandrakasan:
Modeling and sizing for minimum energy operation in subthreshold circuits. 1778-1786 - Hamid Mahmoodi, Saibal Mukhopadhyay, Kaushik Roy:
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits. 1787-1796 - Simon Kristiansson, Fredrik Ingvarson, Shiva Prasad Kagganti, Nebojsa Simic, Marinel Zgrda, Kjell O. Jeppson:
A surface potential model for predicting substrate noise coupling in integrated circuits. 1797-1803 - Amit Agarwal, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy:
Process variation in embedded memories: failure analysis and variation aware architecture. 1804-1814 - Jinuk Luke Shin, Bruce Petrick, Mandeep Singh, Ana Sonia Leon:
Design and implementation of an embedded 512-KB level-2 cache subsystem. 1815-1820 - Raúl Blázquez, Puneet P. Newaskar, Fred S. Lee, Anantha P. Chandrakasan:
A baseband processor for impulse ultra-wideband communications. 1821-1828 - Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan:
A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface. 1829-1838 - William Krenik, Dennis D. Buss, Peter Rickert:
Cellular handset integration - SIP versus SOC. 1839-1846 - Cristiano Niclass, Alexis Rochas, Pierre-André Besse, Edoardo Charbon:
Design and characterization of a CMOS 3-D image sensor based on single photon avalanche diodes. 1847-1854 - KiYoung Nam, Sang-Min Lee, David K. Su, Bruce A. Wooley:
A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion. 1855-1864 - Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto:
A delta-sigma modulator for a 1-bit digital switching amplifier. 1865-1871 - Brian Guthrie, John B. Hughes, Tony Sayers, Adrian Spencer:
A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver. 1872-1879 - Brett Forejt, Vijay Rentala, Jose Duilio Arteaga, Gangadhar Burra:
A 700+-mW class D design with direct battery hookup in a 90-nm process. 1880-1887 - Vincent W. Leung, Junxiong Deng, Prasad S. Gudem, Lawrence E. Larson:
Analysis of envelope signal injection for improvement of RF amplifier intermodulation distortion. 1888-1894 - Yongwang Ding, Ramesh Harjani:
A high-efficiency CMOS +22-dBm linear power amplifier. 1895-1900 - Abbas Komijani, Arun Natarajan, Ali Hajimiri:
A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-μm CMOS. 1901-1908 - Sander L. J. Gierkink, Dandan Li, Robert C. Frye, Vito Boccuzzi:
A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver. 1909-1921 - Dimitri Linten, Xiao Sun, Geert Carchon, Wutthinan Jeamsaksiri, Abdelkarim Mercha, Javier Ramos, Snezana Jenei, Piet Wambacq, Morin Dehan, Lars Aspemyr, Andries J. Scholten, Stefaan Decoutere, Stéphane Donnay, Walter De Raedt:
Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors. 1922-1931 - Pengfei Zhang, Lawrence Der, Dawei Guo, Isaac Sever, Taoufik Bourdi, Christopher Lam, Alireza Zolfaghari, Jess Chen, Douglas Gambetta, Baohong Cheng, Sujatha Gowder, Siegfried Hart, Lam Huynh, Thai Nguyen, Behzad Razavi:
A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS. 1932-1939 - Abdulkerim L. Coban, Mustafa H. Koroglu, Kashif A. Ahmed:
A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs. 1940-1947 - Brian S. Leibowitz, Bernhard E. Boser, Kristofer S. J. Pister:
A 256-element CMOS imaging receiver for free-space optical communication. 1948-1956 - Vishnu Balan, Joe Caroselli, Jenn-Gang Chern, Catherine Chow, Ratnakar Dadi, Chintan Desai, Leo Fang, David Hsu, Pankaj Joshi, Hiroshi Kimura, Cathy Ye Liu, Tzu-Wang Pan, Ryan Park, Cindy You, Yi Zeng, Eric Zhang, Freeman Zhong:
A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization. 1957-1967 - Rony E. Amaya, Peter H. R. Popplewell, Mark Cloutier, Calvin Plett:
EM and substrate coupling in silicon RFICs. 1968-1971 - Gowtham Vemulapalli, Pavan Kumar Hanumolu, Youn-Jae Kook, Un-Ku Moon:
A 0.8-V accurately tuned linear continuous-time filter. 1972-1977 - Jonne Lindeberg, Jouko Vankka, Johan Sommarek, Kari Halonen:
A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-μm CMOS. 1978-1982 - Ranjit Gharpurey:
A broadband low-noise front-end amplifier for ultra wideband in 0.13-μm CMOS. 1983-1986 - Sergey V. Rylov, Scott K. Reynolds, Daniel W. Storaska, Brian A. Floyd, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, Michael Sorna:
10+ gb/s 90-nm CMOS serial link demo in CBGA package. 1987-1991
Volume 40, Number 10, October 2005
- David J. Walkey:
Introduction to the Special Issue on the IEEE Bipolar/BiCMOS Circuits and Technology Meeting. 1995-1996 - Drew Guckenberger, Kevin T. Kornegay:
Design of a differential distributed amplifier and oscillator using close-packed interleaved transmission lines. 1997-2007 - Hugo Veenstra, G. A. M. Hurkx, Dave van Goor, Hans Brekelmans, John R. Long:
Analyses and design of bias circuits tolerating output voltages above BVCEO. 2008-2018 - Francesco Carrara, Giuseppe Palmisano:
High-dynamic-range VGA with temperature compensation and linear-in-dB gain control. 2019-2024 - Pascal Chevalier, Cyril Fellous, Laurent Rubaldo, Franck Pourchon, Sébastien Pruvost, Rudy Beerkens, Fabienne Saguin, Nicolas Zerounian, Benoît Barbalat, Sylvie Lépilliet, Didier Dutartre, Didier Céli, Isabelle Telliez, Daniel Gloria, Frédéric Aniel, François Danneville, Alain Chantre:
230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications. 2025-2034 - Wolfgang Steiner, Hans-Martin Rein, Jürgen Berntgen:
Substrate coupling in a high-gain 30-Gb/s SiGe amplifier-modeling, suppression, and measurement. 2035-2045 - Mounir Meghelli:
A 43-Gb/s full-rate clock transmitter in 0.18-μm SiGe BiCMOS technology. 2046-2050 - Kevin T. Kornegay, Joy Laskar:
Introduction to the Special Issue on the First IEEE Compound Semiconductor Integrated Circuits Symposium (CSICS). 2051-2053 - Akio Wakejima, Takahiro Asano, Takafumi Hirano, Masahiro Funabashi, Kohji Matsunaga:
C-band GaAs FET power amplifiers with 70-W output power and 50% PAE for satellite communication use. 2054-2060 - Zach Griffith, Yingda Dong, Dennis W. Scott, Yun Wei, Navin Parthasarathy, Mattias Dahlström, Christoph Kadow, Vamsi Paidi, Mark J. W. Rodwell, Miguel Urteaga, Richard Pierson, Petra Rowell, Bobby Brar, Sangmin Lee, Nguyen X. Nguyen, Chahn Nguyen:
Transistor and circuit design for 100-200-GHz ICs. 2061-2069 - Axel Tessmann:
220-GHz metamorphic HEMT amplifier MMICs for high-resolution imaging applications. 2070-2076 - Herbert Zirath, Rumen Kozhuharov, Mattias Ferndahl:
Balanced Colpitt oscillator MMICs designed for ultra-low phase noise. 2077-2086 - Giuseppe De Astis, David Cordeau, Jean-Marie Paillot, Lucian Dascalescu:
A 5-GHz fully integrated full PMOS low-phase-noise LC VCO. 2087-2091 - Brian Welch, Kevin T. Kornegay, Hyun-Min Park, Joy Laskar:
20-GHz low-noise amplifier with active balun in a 0.25-μm SiGe BICMOS technology. 2092-2097 - Yusuke Inoue, Masaru Sato, Toshihiro Ohki, Kozo Makiyama, Tsuyoshi Takahashi, Hisao Shigematsu, Tatsuya Hirose:
A 90-GHz InP-HEMT lossy match amplifier with a 20-dB gain using a broadband matching technique. 2098-2103 - Thomas W. Crowe, William L. Bishop, David W. Porterfield, Jeffrey L. Hesler, Robert M. Weikle:
Opening the terahertz window with integrated diode circuits. 2104-2110 - Yasushi Amamiya, Zin Yamazaki, Yasuyuki Suzuki, Masayuki Mamada, Hikaru Hida:
Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry. 2111-2117 - Herbert Knapp, Martin Wurzer, Werner Perndl, Klaus Aufinger, Josef Böck, Thomas F. Meister:
100-Gb/s 27-1 and 54-Gb/s 211-1 PRBS generators in SiGe bipolar technology. 2118-2125
Volume 40, Number 11, November 2005
- Keerthiraj Nagaraj:
Editorial. 2131 - Guangyu Evelina Zhang, Michael M. Green:
A 10 Gb/s BiCMOS adaptive cable equalizer. 2132-2140 - Nestoras Tzartzanis, William W. Walker:
Differential current-mode sensing for efficient on-chip global signaling. 2141-2147 - Hyung-Rok Lee, Moon-Sang Hwang, Bong-Joon Lee, Young-Deok Kim, Dohwan Oh, Jaeha Kim, Sang-Hyun Lee, Deog-Kyoon Jeong, Wonchan Kim:
A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique. 2148-2158 - Holly Pekau, James W. Haslett:
A 2.4 GHz CMOS sub-sampling mixer with integrated filtering. 2159-2166 - Juo-Jung Hung, Timothy M. Hancock, Gabriel M. Rebeiz:
A 77 GHz SiGe sub-harmonic balanced mixer. 2167-2173 - Sten E. Gunnarsson, Camilla Kärnfelt, Herbert Zirath, Rumen Kozhuharov, Dan Kuylenstierna, Arne Alping, Christian Fager:
Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology. 2174-2186 - Yong-Hsiang Hsieh, Wei-Yi Hu, Shin-Ming Lin, Chao-Liang Chen, Wen-Kai Li, Sao-Jie Chen, David J. Chen:
An auto-I/Q calibrated CMOS transceiver for 802.11g. 2187-2192 - Jari-Pascal Curty, Norbert Joehl, Catherine Dehollain, Michel J. Declercq:
Remotely powered addressable UHF RFID integrated system. 2193-2202 - Robert Bogdan Staszewski, Chih-Ming Hung, Nathen Barton, Meng-Chang Lee, Dirk Leipold:
A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones. 2203-2211 - Mohammad Maymandi-Nejad, Manoj Sachdev:
A monotonic digitally controlled delay element. 2212-2219 - Davide De Caro, Antonio Giuseppe Maria Strollo:
High-performance direct digital frequency synthesizers in 0.25 μm CMOS using dual-slope approximation. 2220-2227 - Hyungki Huh, Yido Koo, Kang-Yoon Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer. 2228-2236 - Marco Berkhout:
Integrated overcurrent protection system for class-D audio power amplifiers. 2237-2245 - José M. de la Rosa, Sara Escalera, Belén Pérez-Verdú, Fernando Medeiro, Oscar Guerra, Rocío del Río, Ángel Rodríguez-Vázquez:
A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs. 2246-2264 - Chi Yat Leung, Philip K. T. Mok, Ka Nang Leung:
A 1-V integrated current-mode boost converter in standard 3.3/5-V CMOS technologies. 2265-2274 - Daniel Sun, Andrea Xotta, Asad A. Abidi:
A 1 GHz CMOS analog front-end for a generalized PRML read channel. 2275-2285 - Udo Karthaus, Stefan Schabel:
Write pulse Generator for 16x DVD recording with symmetric CMOS inverter ring oscillator. 2286-2295 - Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto:
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. 2296-2304 - Isao Takayanagi, Miho Shirakawa, Koji Mitani, Masayuki Sugawara, Steinar Iversen, Jørgen Moholt, Junichi Nakamura, Eric R. Fossum:
A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor. 2305-2314 - Thomas Nirmaier, Cristina Alvarez Diez, Josef F. Bille:
High-speed CMOS wavefront sensor with resistive-ring networks of winner-take-all circuits. 2315-2322 - Zhenbiao Li, Kenneth K. O:
15-GHz fully integrated nMOS switches in a 0.13-μm CMOS process. 2323-2328 - Ming-Dou Ker, Kun-Hsien Lin:
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology. 2329-2338 - Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu:
Correction to "A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration". 2339 - Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". 2339
Volume 40, Number 12, December 2005
- Axel Thomsen, Jacques Christophe Rudell, Yuriy M. Greshishchev, J. E. D. Hurwitz:
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference. 2359-2363 - Bhupendra K. Ahuja, Hoa Vu, Carlos A. Laber, William H. Owen:
A very high precision 500-nA CMOS floating-gate analog voltage reference. 2364-2372 - Shouri Chatterjee, Yannis P. Tsividis, Peter R. Kinget:
0.5-V analog circuit techniques and their application in OTA and filter design. 2373-2387 - Eric Gaalaas, Bill Yang Liu, Naoaki Nishimura, Robert Adams, Karl Sweetland:
Integrated stereo ΔΣ class D amplifier. 2388-2397 - Gil-Cho Ahn, Dong-Young Chang, Matthew E. Brown, Naoto Ozaki, Hiroshi Youra, Ken Yamamura, Koichi Hamashita, Kaoru Takasuka, Gábor C. Temes, Un-Ku Moon:
A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. 2398-2407 - Khiem Nguyen, Robert Adams, Karl Sweetland, Huaijin Chen:
A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio. 2408-2415 - Lukas Dörrer, Franz Kuttner, Patrizia Greco, Patrick Torta, Thomas Hartig:
A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS. 2416-2427 - Jiang Yu, Franco Maloberti:
A low-power multi-bit ΣΔ modulator in 90-nm digital CMOS without DEM. 2428-2436 - John A. McNeill, Michael C. W. Coln, Brian J. Larivee:
"Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. 2437-2445 - Imran Ahmed, David A. Johns:
A 50-MS/s (35 mW) to 1-kS/s (15 μW) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation. 2446-2455 - Myung-Jun Choe, Kwang-Hyun Baek, Mesfin Teshome:
A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation. 2456-2468 - Robert Bogdan Staszewski, John L. Wallberg, Sameh Rezeq, Chih-Ming Hung, Oren E. Eliezer, Sudheer K. Vemulapalli, Chan Fernando, Ken Maggio, Roman Staszewski, Nathen Barton, Meng-Chang Lee, Patrick Cruise, Mitch Entezari, Khurram Muhammad, Dirk Leipold:
All-digital PLL and transmitter for mobile phones. 2469-2482 - Srenik S. Mehta, David Weber, Manolis Terrovitis, Keith Onodera, Michael P. Mack, Brian J. Kaczynski, Hirad Samavati, Steve Hung-Min Jen, William Weimin Si, MeeLan Lee, Kalwant Singh, Sunetra Mendis, Paul J. Husted, Ning Zhang, Bill McFarland, David K. Su, Teresa H. Meng, Bruce A. Wooley:
An 802.11g WLAN SoC. 2483-2491 - Shahla Khorram, Hooman Darabi, Zhimin Zhou, Qiang (Tom) Li, Bojko Marholev, Janice Chiu, Jesse Castaneda, Hung-Ming (Ed) Chien, Seema Butala Anand, Stephen Wu, Meng-An Pan, Razieh Roofougaran, Hea Joung Kim, Paul Lettieri, Brima Ibrahim, Jacob J. Rael, Long H. Tran, E. Geronaga, H. Yeh, T. Frost, Jason Trachewsky, Ahmadreza Rofougaran:
A fully integrated SOC for 802.11b in 0.18-μm CMOS. 2492-2501 - Arun Natarajan, Abbas Komijani, Ali Hajimiri:
A fully integrated 24-GHz phased-array transmitter in CMOS. 2502-2514 - Jeyanandh Paramesh, Ralph Bishop, Krishnamurthy Soumyanath, David J. Allstot:
A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity. 2515-2524 - Chun-Huat Heng, Manoj Gupta, Sang-Hoon Lee, David Kang, Bang-Sup Song:
A CMOS TV tuner/demodulator IC with digital image rejection. 2525-2535 - Patrick Antoine, Philippe Bauser, Hugues Beaulaton, Martin Buchholz, Declan Carey, Thierry Cassagnes, T. K. Chan, Stephane Colomines, Fionn Hurley, David T. Jobling, Niall Kearney, Aidan C. Murphy, James Rock, Didier Salle, Cao-Thong Tu:
A direct-conversion receiver for DVB-H. 2536-2546 - Shwetabh Verma, Junfeng Xu, Mototsugu Hamada, Thomas H. Lee:
A 17-mW 0.66-mm2 direct-conversion receiver for 1-Mb/s cable replacement. 2547-2554 - Behzad Razavi, Turgut Aytur, Christopher Lam, Fei-Ran Yang, Kuang-Yu (Jason) Li, Ran-Hong (Ran) Yan, Han-Chang Kang, Cheng-Chung Hsu, Chao-Cheng Lee:
A UWB CMOS transceiver. 2555-2562 - Raf Roovers, Domine M. W. Leenaerts, Jos Bergervoet, Kundur S. Harish, Remco C. H. van de Beek, Gerard van der Weide, Helen Waite, Yifeng Zhang, Sudhir Aggarwal, Charles J. Razzell:
An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology. 2563-2572 - Aly Ismail, Asad A. Abidi:
A 3.1- to 8.2-GHz zero-IF receiver and direct frequency synthesizer in 0.18-μm SiGe BiCMOS for mode-2 MB-OFDM UWB communication. 2573-2582 - Tak Shun Dickson Cheung, John R. Long:
A 21-26-GHz SiGe bipolar power amplifier MMIC. 2583-2597 - Patrick Reynaert, Michiel S. J. Steyaert:
A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE. 2598-2608 - Xiaoyong Li, Sudip Shekhar, David J. Allstot:
Gm-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-μm CMOS. 2609-2619 - Davide Guermandi, Paola Tortori, Eleonora Franchi, Antonio Gnudi:
A 0.83-2.5-GHz continuously tunable quadrature VCO. 2620-2627 - Hooman Darabi, Janice Chiu:
A noise cancellation technique in active RF-CMOS mixers. 2628-2632 - Troy J. Beukema, Michael Sorna, Karl Selander, Steven Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes:
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization. 2633-2645 - Robert Payne, Paul E. Landman, Bhavesh Bhakta, Sridhar Ramaswamy, Song Wu, John D. Powers, M. Ulvi Erdogan, Ah-Lyan Yee, Richard Gu, Lin Wu, Yiqun Xie, Bharadwaj Parthasarathy, Keith C. Brouse, Wahed Mohammed, Keerthi Heragu, Vikas Gupta, Lisa Dyson, Wai Lee:
A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels. 2646-2657 - Kannan Krishna, David A. Yokoyama-Martin, Aaron Caffee, Chris Jones, Mat Loikkanen, James Parker, Ross Segelken, Jeff L. Sonntag, John T. Stonick, Steve Titus, Daniel Weinlader, Skye Wolfer:
A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture. 2658-2666 - Christian Kromer, Gion Sialm, Christoph Berger, Thomas Morf, Martin L. Schmatz, Frank Ellinger, Daniel Erni, Gian-Luca Bona, Heinz Jäckel:
A 100-mW 4×10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects. 2667-2679 - Makoto Nakamura, Yuki Imai, Yohtaro Umeda, Jun Endo, Yuji Akatsu:
1.25-Gb/s burst-mode receiver ICs with quick response for PON systems. 2680-2688 - Behnam Analui, Alexander V. Rylyakov, Sergey V. Rylov, Mounir Meghelli, Ali Hajimiri:
A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS. 2689-2699 - Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin L. Schmatz, Jonas R. M. Weiss:
A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links. 2700-2712 - Declan Dalton, Kwet Chai, Eric Evans, Mark A. Ferriss, Dave Hitchcox, Paul Murray, Sivanendra Selvanayagam, Paul Shepherd, Lawrence DeVito:
A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback. 2713-2725 - Jerry (Heng-Chih) Lin:
A low-phase-noise 0.004-ppm/step DCXO with guaranteed monotonicity in the 90-nm CMOS process. 2726-2734 - Timothy O. Dickson, Ekaterina Laskin, Imran Khalid, Rudy Beerkens, Jingqiong Xie, Boris Karajica, Sorin P. Voinigescu:
An 80-Gb/s 231-1 pseudorandom binary sequence generator in SiGe BiCMOS technology. 2735-2745 - Andrew R. Chen, Akintunde Ibitayo (Tayo) Akinwande, Hae-Seung Lee:
CMOS-based microdisplay with calibrated backplane. 2746-2755 - Marshall J. Bell:
An LCD column driver using a switch capacitor DAC. 2756-2765 - Lester J. Kozlowski, Giuseppe Rossi, Laurent Blanquart, Roberto Marchesini, Ying Huang, Gregory Chow, John Richardson, David L. Standley:
Pixel noise suppression via SoC management of tapered reset in a 1920×1080 CMOS image sensor. 2766-2776 - Steven M. Martin, Fadi H. Gebara, Brian J. Larivee, Richard B. Brown:
A CMOS-integrated microinstrument for trace detection of heavy metals. 2777-2786 - Mitsuhito Mase, Shoji Kawahito, Masaaki Sasaki, Yasuo Wakamori, Masanori Furuta:
A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters. 2787-2795 - Roy H. Olsson III, Kensall D. Wise:
A three-dimensional neural recording microsystem with implantable data compression circuitry. 2796-2804 - Michiel A. P. Pertijs, Kofi A. A. Makinwa, Johan H. Huijsing:
A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.1°C from -55°C to 125°C. 2805-2815 - Yukinobu Sugiyama, Munenori Takumi, Haruyoshi Toyoda, Naohisa Mukozaka, Atsushi Ihori, Takayuki Kurashina, Yosuke Nakamura, Takashi Tonbe, Seiichiro Mizuno:
A high-speed CMOS image sensor with profile data acquiring function. 2816-2823
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