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ORCIDIEEE Journal of Solid-State Circuits, Volume 40
Volume 40, Number 1, January 2005
- Georgios K. Konstadinidis, Anantha P. Chandrakasan, Sreedhar Natarajan, Thucydides Xanthopoulos:
Introduction to the Special Issue on the ISSCC2004. 3-6 - Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Howard Levy, Ha Pham, Jinseung Son, Nathan Moon, Dina Bistry, Umesh Nair, Mandeep Singh, Vikas Mathur, Ana Sonia Leon:
A dual-core 64-bit ultraSPARC microprocessor for dense server applications. 7-18 - Norman J. Rohrer, Cédric Lichtenau, Peter A. Sandon, Paul Kartschoke, Erwin B. Cohen, Miles G. Canada, Thomas Pflüger, Mathew I. Ringler, Rolf B. Hilgendorf, Stephen F. Geissler, Jeffrey S. Zimmerman:
A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features. 19-27 - Masakatsu Nakai, Satoshi Akui, Katsunori Seno, Tetsumasa Meguro, Takahiro Seki, Tetsuo Kondo, Akihiko Hashiguchi, Hirokazu Kawahara, Kazuo Kumano, Masayuki Shimura:
Dynamic voltage and frequency management for a low-power embedded microprocessor. 28-35 - Daniel J. Deleganes, Micah Barany, George L. Geannopoulos, Kurt Kreitzer, Matthew Morrise, Dan Milliron, Anant P. Singh, Sapumal B. Wijeratne:
Low-voltage swing logic circuits for a Pentium® 4 processor integer core. 36-43 - Sanu K. Mathew, Mark A. Anders, Brad Bloechel, Trang Nguyen, Ram K. Krishnamurthy, Shekhar Borkar:
A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS. 44-51 - Hugh McIntyre, Dennis Wendell, K. James Lin, P. Kaushik, Suresh Seshadri, Alfred Wang, V. Sundararaman, Ping Wang, Song Kim, Wen-Jay Hsu, Hee-Choul Park, Gideon Levinsky, Jiejun Lu, M. Chirania, Raymond A. Heald, Paul Lazar, Sanjaya Dharmasena:
A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor. 52-59 - Masaya Sumita, Shiro Sakiyama, Masayoshi Kinoshita, Yuta Araki, Yuichiro Ikeda, Kohei Fukuoka:
Mixed body bias techniques with fixed Vt and Ids generation circuits. 60-66 - Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi:
An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs. 67-79 - James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan Casper, Aaron Martin, Joseph T. Kennedy, Naresh R. Shanbhag, Randy Mooney:
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew. 80-88 - Jin-Hyun Kim, Sua Kim, Woo-Seop Kim, Jung-Hwan Choi, Hong-Sun Hwang, Changhyun Kim, Suki Kim:
A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling. 89-101 - Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle:
Uniform-phase uniform-amplitude resonant-load global clock distributions. 102-109 - (Withdrawn) Notice of Violation of IEEE Publication Principles: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation. 110-131
- Anne-Johan Annema
, Bram Nauta, Ronald van Langevelde, Hans Tuinhout:
Analog circuits in ultra-deep-submicron CMOS. 132-143 - Chinh H. Doan, Sohrab Emami, Ali M. Niknejad, Robert W. Brodersen:
Millimeter-wave CMOS design. 144-155 - Brian A. Floyd, Scott K. Reynolds, Ullrich R. Pfeiffer, Thomas Zwick, Troy J. Beukema, Brian P. Gaucher:
SiGe bipolar transceiver circuits operating at 60 GHz. 156-167 - Shunichi Kaeriyama, Toshitsugu Sakamoto, Hiroshi Sunamura, Masayuki Mizuno, Hisao Kawaura, Tsuyoshi Hasegawa, Kazuya Terabe, Tomonobu Nakayama, Masakazu Aono:
A nonvolatile programmable solid-electrolyte nanometer switch. 168-176 - Hiroshi Kawaguchi, Takao Someya, Tsuyoshi Sekitani, Takayasu Sakurai:
Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin. 177-185 - Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada:
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. 186-194 - Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni:
A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. 195-203 - Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. 204-212 - John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva:
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. 213-222 - Sang-Bo Lee, Seong-Jin Jang, Jin-Seok Kwak, Sang-Jun Hwang, Young-Hyun Jun, Soo-In Cho, Chil-Gee Lee:
A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. 223-232 - Joseph T. Kennedy, Randy Mooney, Robert Ellis, James E. Jaussi, Shekhar Borkar, Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Steffen Loeffler, Jochen Hoffmann, Wolfgang Hokenmaier, Russ Houghton, Thomas Vogelsang:
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. 233-244 - Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. 245-253 - Sungdae Choi, Kyomin Sohn, Hoi-Jun Yoo:
A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture. 254-260 - Ken Mai, Ron Ho, Elad Alon, Dean Liu, Younggon Kim, Dinesh Patil, Mark A. Horowitz:
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS. 261-275 - Shigeru Nakahara, Takahiro Kawata:
A design for a minimum Hamming-distance search using asynchronous digital techniques. 276-285 - Kunisato Yamaoka, Shunichi Iwanari, Yasuo Murakuki, Hiroshige Hirano, Masahiko Sakagami, Tetsuji Nakakuma, Takashi Miki, Yasushi Gohou:
A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure. 286-292 - Woo Yeong Cho, Beak-Hyung Cho, Byung-Gil Choi, Hyung-Rok Oh, Sangbeom Kang, Ki-Sung Kim, Kyung-Hee Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Youngnam Hwang, SuJin Ahn, Gwan-Hyeob Koh, Gitae Jeong, Hongsik Jeong, Kinam Kim:
A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM). 293-300 - Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian, Bradley J. Garni, Halbert S. Lin, Asim Omair, William L. Martino:
A 4-Mb 0.18-μm 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers. 301-309 - Alice Wang, Anantha P. Chandrakasan:
A 180-mV subthreshold FFT processor using a minimum energy design methodology. 310-319 - David Garrett, Graeme K. Woodward, Linda M. Davis, Chris Nicol:
A 28.8 Mb/s 4 × 4 MIMO 3G CDMA receiver for frequency selective channels. 320-330 - Hideki Yamauchi, Shigeyuki Okada, Kazuhiko Taketa, Yuh Matsuda, Tsugio Mori, Tsuyoshi Watanabe, Yoshihiro Matsuo, Yoshifumi Matsushita:
1440 × 1080 pixel, 30 frames per second motion-JPEG 2000 codec for HD-movie transmission. 331-341 - Goang Seog Choi, Joo Seon Kim, Hyun Jeong Park, Young Jun Ahn, Hyun Soo Park, Jum Han Bae, In Sik Park, Dong Ho Shin:
A 0.18-μm CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML. 342-350
Volume 40, Number 2, February 2005
- Krishnaswamy Nagaraj:
New Associate Editor. 359 - Albert C. Jerng, Charles G. Sodini:
The impact of device type and sizing on phase noise mechanisms. 360-369 - Burcin Baytekin, Robert G. Meyer:
Analysis and simulation of spectral regrowth in radio frequency power amplifiers. 370-381 - Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Mayaram, Terri S. Fiez:
Simulation and measurement of supply and substrate noise in mixed-signal ICs. 382-391 - Ilku Nam, Kwyro Lee:
High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology. 392-402 - Yann Le Guillou, Olivier Gaborieau, Patrice Gamand, Martin Isberg, Peter Jakobsson, Lars Jonsson, David Le Déaut, Hervé Marie, Sven Mattisson, Laurent Monge, Torbjörn Olsson, Sébastien Prouet, Tobias Tired:
Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time ΣΔ ADC. 403-411 - Andreas Demosthenous, Iasonas F. Triantis:
An adaptive ENG amplifier for tripolar cuff electrodes. 412-421 - Arun Rao, William McIntyre, Un-Ku Moon, Gábor C. Temes:
Noise-shaping techniques applied to switched-capacitor voltage regulators. 422-429 - Julius Georgiou, Christopher Toumazou:
A 126-μW cochlear chip for a totally implantable system. 430-443 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A 375 × 365 high-speed 3-D range-finding image sensor using row-parallel search architecture and multisampling technique. 444-453 - Michiel A. P. Pertijs, Andrea Niederkorn, Xu Ma, Bill McKillop, Anton Bakker, Johan H. Huijsing:
A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.5°C from -50°C to 120°C. 454-461 - Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. Conroy, Beomsup Kim:
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer. 462-471 - Mingdeng Chen, Jose Silva-Martinez, Michael Nix, Moises E. Robinson:
Low-voltage low-power LVDS drivers. 472-479 - Woopyo Jeong, Kaushik Roy:
High-performance low-power dual transition preferentially sized (DTPS) logic. 480-484 - Steven J. E. Wilton, Noha Kafafi, James C. H. Wu, Kimberly A. Bozman, Victor O. Aken'Ova, Resve Saleh:
Design considerations for soft embedded programmable logic cores. 485-497 - Lawrence T. Clark, Franco Ricci, Manish Biyani:
Low standby power state storage for sub-130-nm technologies. 498-506 - Antonino Conte, Gianbattista Lo Giudice, Gaetano Palumbo, Alfredo Signorello:
A high-performance very low-voltage current sense amplifier for nonvolatile memories. 507-514 - Chiu-Chiao Chung, Hongchin Lin, Yen-Tai Lin:
A novel high-speed sense amplifier for Bi-NOR flash memories. 515-522 - Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara:
Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories. 523-531 - Xicheng Jiang, Mau-Chung Frank Chang:
A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging. 532-535 - Maziar Tavakoli, Rahul Sarpeshkar:
A sinh resistor and its application to tanh linearization. 536-543 - Chang-Wan Kim, Min-Suk Kang, Phan Tuan Anh, Hoon-Tae Kim, Sang-Gug Lee:
An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system. 544-547 - Chia-Hsin Wu, Chih-Hun Lee, Wei-Sheng Chen, Shen-Iuan Liu:
CMOS wideband amplifiers using multiple inductive-series peaking technique. 548-552 - Frank Ellinger:
60-GHz SOI CMOS traveling-wave amplifier with NF below 3.8 dB from 0.1 to 40 GHz. 553-558 - Jri Lee, Behzad Razavi:
Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology". 559 - Sudhakar Pamarti, Lars C. Jansson, Ian Galton:
Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation". 559
Volume 40, Number 3, March 2005
- Krishnaswamy Nagaraj:
New Associate Editor. 575 - Bert Serneels, Tim Piessens, Michiel Steyaert, Wim Dehaene:
A high-voltage output driver in a 2.5-V 0.25-μm CMOS technology. 576-583 - Xiaohua Fan, Chinmaya Mishra, Edgar Sánchez-Sinencio:
Single Miller capacitor frequency compensation technique for low-power multistage amplifiers. 584-592 - Xiaofeng Lin, Sooping Saw, Jin Liu:
A CMOS 0.25-μm continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission. 593-602 - Todd S. Kaplan, Joseph F. Jensen, Charles H. Fields, Mau-Chung Frank Chang:
A 2-GS/s 3-bit ΔΣ-modulated DAC with tunable bandpass mismatch shaping. 603-610 - Angelo Scuderi, Luca La Paglia, Antonino Scuderi, Francesco Carrara, Giuseppe Palmisano:
A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control. 611-621 - Karim W. Hamed, Alois P. Freundorfer, Yahia M. M. Antar:
A monolithic double-balanced direct conversion mixer with an integrated wideband passive balun. 622-629 - Reza Navid, Thomas H. Lee, Robert W. Dutton:
Minimum achievable phase noise of RC oscillators. 630-637 - William F. Andress, Donhee Ham:
Standing wave oscillators utilizing wave-adaptive tapered transmission lines. 638-651 - KaChun Kwok, Howard C. Luong:
Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback. 652-660 - Hsiang-Hui Chang, Shen-Iuan Liu:
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop. 661-670 - Ken Yamamoto, Minoru Fujishima:
A 44-μW 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range. 671-677 - John W. M. Rogers, Foster F. Dai, Mark S. Cavin, David G. Rahn:
A multiband ΔΣ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC. 678-689 - Paolo Rossi, Antonio Liscidini, Massimo Brandolini, Francesco Svelto:
A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications. 690-697 - Hooman Darabi, Janice Chiu, Shahla Khorram, Hea Joung Kim, Zhimin Zhou, Hung-Ming (Ed) Chien, Brima Ibrahim, E. Geronaga, Long H. Tran, Ahmadreza Rofougaran:
A dual-mode 802.11b/bluetooth radio in 0.35-μm CMOS. 698-706 - Spyros Pipilos, Yannis Papananos, Nikolaos Naskas, Manolis Zervakis, Jakob Jongsma, Tony Gschier, Nigel Wilson, Jo Gibbins, Bob Carter, Graham Dann:
A transmitter IC for TETRA systems based on a Cartesian feedback loop linearization technique. 707-718 - Makoto Takamiya, Masayuki Mizuno:
A 6.7-fF/μm2 bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL. 719-725 - Kwangseok Han, Joonho Gil, Seong-Sik Song, Jeonghu Han, Hyungcheol Shin, Choong-Ki Kim, Kwyro Lee:
Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier. 726-735 - Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama, Hubert Siedhoff:
A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator. 736-743 - Ehsan Afshari, Ali Hajimiri:
Nonlinear transmission lines for pulse shaping in silicon. 744-752 - Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, Sergio Benedetto:
A 0.35-μm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code. 753-762 - Mohanasankar Sivaprakasam, Wentai Liu, Mark S. Humayun, James D. Weiland:
A variable range bi-phasic current stimulus driver circuitry for an implantable retinal prosthetic device. 763-771 - Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui:
A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation. 772-780 - Kenneth W. H. Ng, Vincent S. L. Cheung, Howard C. Luong:
A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques. 781-784 - Kenneth W. H. Ng, Vincent S. L. Cheung, Howard C. Luong:
A 28-MHz wideband switched-capacitor bandpass filter with transmission zeros for high attenuation. 785-790 - Toru Masuda, Kenichi Ohhata, Nobuhiro Shiramizu, Eiji Ohue, Katsuya Oda, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Takashi Harada, Katsuyoshi Washio:
SiGe-HBT-based 54-gb/s 4: 1 multiplexer IC with full-rate clock for serial communication systems. 791-795 - Jong K. Kim, Thottam S. Kalkur:
High-speed current-mode logic amplifier using positive feedback and feed-forward source-follower techniques for high-speed CMOS I/O buffer. 796-802 - Jose Alfredo Tirado-Mendez, Hildeberto Jardón-Aguilar:
Comments on "On unilateral dual feedback low-noise amplifier with simultaneous noise, impedance, and IIP3 Match". 803
Volume 40, Number 4, April 2005
- Bruce Gieseke, Tadahiro Kuroda:
Introduction to the Special Issue. 811-812 - Makoto Nagata, Takeshi Okumoto, Kazuo Taki:
A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits. 813-819 - Elad Alon, Vladimir Stojanovic, Mark A. Horowitz:
Circuits and techniques for high-resolution measurement of on-chip power supply noise. 820-828 - Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda:
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. 829-837 - Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar:
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. 838-845 - Saravanan Rajapandian, Zheng Xu, Kenneth L. Shepard:
Implicit DC-DC downconversion through charge-recycling. 846-852 - Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara:
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. 853-861 - Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi:
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. 862-869 - Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh:
A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. 870-876 - Myoung-Kyu Seo, Soung-Hoon Sim, Myoung-Hee Oh, Hyo-Sang Lee, Sang-Won Kim, In-Wook Cho, Gyu-Hong Kim, Moon-Gone Kim:
A 130-nm 0.9-V 66-MHz 8-Mb (256K × 32) local SONOS embedded flash EEPROM. 877-883 - Wing K. Luk, Robert H. Dennard:
A novel dynamic memory cell with internal voltage gain. 884-894 - Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr:
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. 895-901 - Dietmar Gogl, Christian Arndt, John C. Barwin, Alexander Bette, John K. DeBrosse, Earl T. Gow, Heinz Hoenigschmid, Stefan Lammers, Mark C. Lamorey, Yu Lu, Tom Maffitt, Kim Maloney, Werner Obermaier, Andre Sturm, Hans Viehmann, Dennis R. Willmott, Mark A. Wood, William J. Gallagher, Gerhard Mueller, Arkalgud R. Sitaram:
A 16-Mb MRAM featuring bootstrapped write drivers. 902-908 - Axel D. Berny, Ali M. Niknejad, Robert G. Meyer:
A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration. 909-917 - Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators. 918-925 - Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata:
A low-power and compact CDMA matched filter based on switched-current technology. 926-932 - Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar:
Area-efficient linear regulator with ultra-fast load regulation. 933-940 - Shiro Dosho, Naoshi Yanagisawa, Akira Matsuzawa:
A background optimization method for PLL by measuring phase jitter performance. 941-950 - Diego Barrettino, Sadik Hafizovic, Tormod Volden, Jan Sedivý, Kay-Uwe Kirstein, Andreas Hierlemann:
CMOS monolithic mechatronic microsystem for surface imaging and force response studies. 951-959 - Jipeng Li, Gil-Cho Ahn, Dong-Young Chang, Un-Ku Moon:
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR. 960-969 - Mario Valla, Giampiero Montagna, Rinaldo Castello, Riccardo Tonietto, Ivan Bietti:
A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner. 970-977