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ORCIDIEEE Journal of Solid-State Circuits, Volume 38
Volume 38, Number 1, January 2003
- Alexander Schild, Hans-Martin Rein, Jens Müllrich, Lars Altenhain, Jürgen Blank, Karl Schrödinger:
High-gain SiGe transimpedance amplifier array for a 12×10 Gb/s parallel optical-fiber link. 4-12 - Jafar Savoj, Behzad Razavi:
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector. 13-21 - Tim Piessens
, Michiel Steyaert:
Highly efficient xDSL line drivers in 0.35-μm CMOS using a self-oscillating power amplifier. 22-29 - Wenjun Sheng, Bo Xia, Ahmed E. Emira, Chunyu Xin, Ari Yakov Valero-López, Sung Tae Moon, Edgar Sánchez-Sinencio:
A 3-V, 0.35-μm CMOS Bluetooth receiver IC. 30-42 - Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver. 43-53 - Chi-Sheng Lin, Bin-Da Liu:
A new successive approximation architecture for low-power low-cost CMOS A/D converter. 54-62 - Christopher D. Salthouse, Rahul Sarpeshkar:
A practical micropower programmable bandpass filter for use in bionic ears. 63-70 - Ugur Çilingiroglu, Adriana Becker-Gomez, Kenton T. Veeder:
An evaluation of MOS interface-trap charge pump as an ultralow constant-current generator. 71-83 - Francisco Serra-Graells, José Luis Huertas:
Sub-1-V CMOS proportional-to-absolute temperature references. 84-88 - Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok:
Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode. 89-100 - Yoshinori Muramatsu, Susumu Kurosawa, Masayuki Furumiya, Hiroaki Ohkubo, Yasutaka Nakashiba:
A signal-processing CMOS image sensor using a simple analog operation. 101-106 - Akira Tanabe, Yasushi Nakahara, Akio Furukawa, Tohru Mogami:
A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC. 107-113 - Chris Binan Wang, Sonny Ishizuka, Bill Yang Liu:
A 113-dB DSD audio ADC using a density-modulated dithering scheme. 114-119 - Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering. 120-125 - Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
DC-coupled IF stage design for a 900-MHz ISM receiver. 126-134 - Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino:
A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology. 135-137 - Rami Ahola, Kari Halonen:
A 1.76-GHz 22.6-mW ΔΣ fractional-n frequency synthesizer. 138-140 - Yuping Toh, John A. McNeill:
Single-ended to differential converter for multiple-stage single-ended ring oscillators. 141-145 - Ka Nang Leung, Philip K. T. Mok:
A CMOS voltage reference based on weighted ΔVGS for CMOS low-dropout linear regulators. 146-150 - Gianluca Giustolisi, Gaetano Palumbo, M. Criscione, F. Cutri:
A low-voltage low-power voltage reference based on subthreshold MOSFETs. 151-154 - Igor Arsovski, Trevis Chandler, Ali Sheikholeslami:
A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme. 155-158 - Yun Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig:
Correction to "A carry-free 54 b x 54 b multiplier using equivalent bit conversion algorithm". 159 - Wolfgang Rülling:
A remark on carry-free binary multiplication. 159-160 - Milos D. Ercegovac, Tomás Lang, Y. Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig:
Comments on "A carry-free 54 b×54 b multiplier using equivalent bit conversion algorithm". 160-161
Volume 38, Number 2, February 2003
- Lawrence Der, Behzad Razavi:
A 2-GHz CMOS image-reject receiver with LMS calibration. 167-175 - Alireza Zolfaghari, Behzad Razavi:
A low-power 2.4-GHz transmitter/receiver CMOS IC. 176-183 - Hao Li, Hans-Martin Rein:
Millimeter-wave VCOs with wide tuning range and low phase noise, fully integrated in a SiGe bipolar production technology. 184-191 - Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata:
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator. 192-197 - Takamoto Watanabe, Shigenori Yamauchi:
An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time. 198-204 - Rola A. Baki, Mourad N. El-Gamal:
A low-power 5-70-MHz seventh-order log-domain filter with programmable boost, group delay, and gain for hard disk drive applications. 205-215 - José Silva-Martínez, Joseph Adut, José Miguel Rocha-Pérez, Moises E. Robinson, Shahriar Rokhsaz:
A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system. 216-225 - Bahram Fotouhi:
An efficient CMOS line driver for 1.544-Mb/s T1 and 2.048-Mb/s E1 applications. 226-236 - Bharath Kumar Thandri, José Silva-Martínez:
A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors. 237-243 - Maziar Tavakoli, Rahul Sarpeshkar:
An offset-canceling low-noise lock-in architecture for capacitive sensing. 244-253 - Chung-Hsun Huang, Jinn-Shyan Wang:
High-performance and power-efficient CMOS comparators. 254-262 - Benoit Provost, Edgar Sánchez-Sinencio:
On-chip ramp generators for mixed-signal BIST and ADC self-test. 263-273 - Ryuichi Hashido, Akihiro Suzuki, Akihiko Iwata, Tatsuki Okamoto, Yukio Satoh, Mitsuo Inoue:
A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method. 274-280 - Eugenio Culurciello, Ralph Etienne-Cummings, Kwabena A. Boahen:
A biomorphic digital image sensor. 281-294 - Ming-Dou Ker, Tung-Yang Chen:
Substrate-triggered ESD protection circuit without extra process modification. 295-302 - Tsuneaki Fuse, Masako Ohta, Motoki Tokumasu, Hiroshige Fujii, Shigeru Kawanaka, Atsushi Kameyama:
A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology. 303-311 - Kevin J. Chen, Guofu Niu:
Logic synthesis and circuit modeling of a programmable logic gate based on controlled quenching of series-connected negative differential resistance devices. 312-318 - Amit Agarwal, Hai Li, Kaushik Roy:
A single-Vt low-leakage gated-ground cache for deep submicron. 319-328 - Jung Pill Kim, Woodward Yang, Han-Yuan Tan:
A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme. 329-337 - John P. Keane, Michael Q. Le, Paul J. Hurst:
Analog timing recovery for a noise-predictive decision-feedback equalizer. 338-342 - Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu:
A fast locking and low jitter delay-locked loop using DHDL. 343-346 - Ching-Che Chung, Chen-Yi Lee:
An all-digital phase-locked loop for high-speed clock generation. 347-351 - John W. M. Rogers, David G. Rahn, Calvin Plett:
A study of digital and analog automatic-amplitude control circuitry for voltage-controlled oscillators. 352-356 - Hans Gustat, Frank Herzel:
Integrated FSK demodulator with very high sensitivity. 357-360 - Yongping Fan, Jeffrey E. Smith:
On-die termination resistors with analog impedance control for standard CMOS technology. 361-364 - Vishnu Balan:
A low-voltage regulator circuit with self-bias to improve accuracy. 365-368 - Daisuke Miyazaki, Shoji Kawahito, Masanori Furuta:
A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture. 369-373
Volume 38, Number 3, March 2003
- Danilo Manstretta, Massimo Brandolini, Francesco Svelto:
Second-order intermodulation mechanisms in CMOS downconverters. 394-406 - Donhee Ham, Ali Hajimiri:
Virtual damping and Einstein relation in oscillators. 407-418 - Yu Cao, Robert A. Groves, Xuejue Huang, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Tsu-Jae King, Chenming Hu:
Frequency-independent equivalent-circuit model for on-chip spiral inductors. 419-426 - David Cassan, John R. Long:
A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS. 427-435 - John T. Stonick, Gu-Yeon Wei, Jeff L. Sonntag, Daniel Weinlader:
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS. 436-443 - Carlos H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun:
Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era. 444-449 - Patrick G. Drennan, Colin C. McAndrew:
Understanding MOSFET mismatch for analog design. 450-456 - Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu:
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. 457-463 - Teemu Salo, Saska Lindfors, Tuomas Hollman, Jere A. M. Järvinen, Kari A. I. Halonen:
80-MHz bandpass ΔΣ modulators for multimode digital IF receivers. 464-474 - Matthew R. Miller, Craig S. Petrie:
A multibit sigma-delta ADC for multimode receivers. 475-482 - Koen Uyttenhove, Jan Vandenbussche, Erik Lauwers, Georges G. E. Gielen, Michiel S. J. Steyaert:
Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter. 483-494 - Masahiro Murakawa, Toshio Adachi, Yoshihiro Niino, Yuji Kasai, Eiichi Takahashi, Kaoru Takasuka, Tetsuya Higuchi:
An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions. 495-502 - Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda:
A 402-output TFT-LCD driver IC with power control based on the number of colors selected. 503-510 - Hoi Lee, Philip K. T. Mok:
Active-feedback frequency-compensation technique for low-power multistage amplifiers. 511-520 - Michele Borgatti, Francesco Lertora, Benoit Forêt, Lorenzo Cali:
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O. 521-529 - Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Mitsuo Saito, Takashi Miyamori, Goichi Ootomo, Masataka Matsui:
A single-chip MPEG-2 codec based on customizable media embedded processor. 530-540 - Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima:
A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories. 541-549 - Robert C. Frye, Sharad Kapur, Robert C. Melville:
A 2-GHz quadrature hybrid implemented in CMOS technology. 550-555 - Ranjit Gharpurey, Naveen Yanduru, Francesco Dantoni, Petteri Litmanen, Guglielmo Sirna, Terry Mayhugh Jr., Charles Lin, Irene Yuanying Deng, Paul Fontaine, Fang Lin:
A direct-conversion receiver for the 3G WCDMA standard. 556-560 - Ka Nang Leung, Philip K. T. Mok, Chi Yat Leung:
A 2-V 23-μA 5.3-ppm/°C curvature-compensated CMOS bandgap voltage reference. 561-564 - Monte Mar, Bert Sullam, Eric Blom:
An architecture for a configurable mixed-signal device. 565-568 - Ingrid Verbauwhede, Patrick Schaumont, Henry Kuo:
Design and performance testing of a 2.29-GB/s Rijndael processor. 569-572
Volume 38, Number 4, April 2003
- Knut Kieschnick, Horst Zimmermann:
High-sensitivity BiCMOS OEIC for optical storage systems. 579-584 - Praveen Kallam, Edgar Sánchez-Sinencio, Aydin Ilker Karsilayan:
An enhanced adaptive Q-tuning scheme for a 100-MHz fully symmetric OTA-based bandpass filter. 585-593 - Jussi Ryynänen, Kalle Kivekäs, Jarkko Jussila, Lauri Sumanen, Aarno Pärssinen, Kari A. I. Halonen:
A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA. 594-602 - June-Ming Hsu:
A 0.18-μm CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter. 603-613 - Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan:
Jitter transfer characteristics of delay-locked loops - theories and design techniques. 614-621 - Stanley Schuster, Peter W. Cook:
Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. 622-630 - Jae-Yoon Sim, Hongil Yoon, Ki-Chul Chun, Hyun-Seok Lee, Sang-Pyo Hong, Kyu-Chan Lee, Jei-Hwan Yoo, Dong-Il Seo, Soo-In Cho:
A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor. 631-640 - Byung-Do Yang, Lee-Sup Kim:
A low-power ROM using charge recycling and charge sharing techniques. 641-653 - Chi-Sheng Lin, Jui-Chuan Chang, Bin-Da Liu:
A low-power precomputation-based fully parallel content-addressable memory. 654-662 - Ahmed Nader Mohieldin, Edgar Sánchez-Sinencio, José Silva-Martínez:
A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector. 663-668 - Choong-Yul Cha, Sang-Gug Lee:
A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance. 669-672 - Hsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu:
A spread-spectrum clock generator with triangular modulation. 673-676 - Chi-Fang Li, Wern-Ho Sheen, Chong-Ren Wang, Yuan-Sun Chu:
A fast multispeed comma-free Reed-Solomon decoder for W-CDMA applications using foldable systolic array architecture. 677-682 - D. George Gata:
Erratum "A 1.1-V 270-μ a mixed-signal hearing aid chip". 683-682 - Pierce Nagle:
Erratum "A wide-band linear amplitude modulator for polar transmitters based on the concept of interleaving delta modulation". 683
Volume 38, Number 5, May 2003
- Shekhar Borkar, Yoshinobu Nakagome:
Guest Editorial. 687 - Sanu Mathew, Mark A. Anders, Ram K. Krishnamurthy, Shekhar Borkar:
A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core. 689-695 - Siva G. Narendra, Ali Keshavarzi, Bradley A. Bloechel, Shekhar Borkar, Vivek De:
Forward body bias for microprocessors in 130-nm technology generation and beyond. 696-701 - Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano:
Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology. 702-708 - Mark A. Anders, Nivruti Rai, Ram K. Krishnamurthy, Shekhar Borkar:
A transition-encoded dynamic bus technique for high-performance interconnects. 709-714 - Shoichi Masui, Tsuzumi Ninomiya, Michiya Oura, Wataru Yokozeki, Kenji Mukaida, Shoichiro Kawashima:
A ferroelectric memory-based secure dynamically programmable gate array. 715-725 - Masanori Fujibayashi, Toshiyuki Nozawa, Takahiro Nakayama, Kenji Mochizuki, Masahiro Konda, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi:
A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture. 726-733 - John Hyde, Todd Humes, Chris Diorio, Mike Thomas, Miguel E. Figueroa:
A 300-MS/s 14-bit digital-to-analog converter in logic CMOS. 734-740 - Yoshiharu Kudoh, Muneo Fukaishi, Masayuki Mizuno:
A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer. 741-746 - Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos:
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. 747-754 - Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar:
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. 755-761 - Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama:
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. 762-768 - Mark Durlam, Peter J. Naji, Asim Omair, Mark Deherrera, John Calder, Jon M. Slaughter, Brad N. Engel, Nicholas D. Rizzo, Greg Grynkewich, Brian Butcher, Clarence Tracy, Ken Smith, Kelly W. Kyler, J. Jack Ren, Jaynal A. Molla, William A. Feil, Rick G. Williams, Saied Tehrani:
A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects. 769-773 - Waleed Khalil, Tsung-Yuan Chang, Xuewen Jiang, Syed R. Naqvi, Babak Nikjou, James Tseng:
A highly integrated analog front-end for 3G. 774-781 - Emad Hegazi, Asad A. Abidi:
A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-μm CMOS. 782-792 - Armin Deiss, Qiuting Huang:
A low-power 200-MHz receiver for wireless hearing aid devices. 793-804 - Vincent Sin-Luen Cheung, Howard C. Luong, Mansun Chan, Wing-Hung Ki:
A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers. 805-816 - Hiroshi Komurasaki, Tomohiro Sano, Tetsuya Heima, Kazuya Yamamoto, Hideyuki Wakada, Ikuo Yasui, Masayoshi Ono, Toshitsugu Miwa, Hisayasu Sato, Takahiro Miki, Naoyuki Kato:
A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications. 817-825 - James W. Tschanz, Siva G. Narendra, Raj Nair, Vivek De:
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors. 826-829 - Goichi Ono, Masayuki Miyazaki:
Threshold-voltage balance for minimum supply operation [LV CMOS chips]. 830-833 - Richard Chang, Niranjan Talwalkar, C. Patrick Yue, S. Simon Wong:
Near speed-of-light signaling over on-chip electrical interconnects. 834-838 - Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De:
A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. 839-842
Volume 38, Number 6, June 2003
- Chun-Huat Heng, Bang-Sup Song:
A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO. 848-854 - Benyong Zhang, Phillip E. Allen, Jeff M. Huard:
A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-μm CMOS. 855-865 - Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez, Sherif H. K. Embabi:
A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier. 866-874 - Arthur Torosyan, Dengwei Fu, Alan N. Willson Jr.:
A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-μm CMOS. 875-887 - Tai-Cheng Lee, Behzad Razavi:
A stabilization technique for phase-locked frequency synthesizers. 888-894