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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 30
Volume 30, Number 1, January 2022
- Massimo Alioto
:
Editorial Opening of the 2022 TVLSI Editorial Year - Connecting Trends From Society to VLSI Systems. 1-4
- Makoto Nagata, Takuji Miki, Noriyuki Miura:
Physical Attack Protection Techniques for IC Chip Level Hardware Security. 5-14 - Tuotian Liao, Lihong Zhang:
High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing. 15-28 - Yue-Ming Wu, Yu-Hsien Kao, Ta-Shun Chu:
A 68-GHz Loss Compensated Distributed Amplifier Using Frequency Interleaved Technique in 65-nm CMOS Technology. 29-39 - Ragh Kuttappa, Longfei Wang, Selçuk Köse, Baris Taskin:
Multiphase Digital Low-Dropout Regulators. 40-50 - Ghassem Jaberipur, Farzad Ghazanfari:
Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations. 51-59 - Nicholas A. Lanzillo, Albert Chu, Prasad Bhosale, Dan J. Dechene:
Power Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes. 60-67 - Priyesh Shukla, Ankith Muralidhar, Nick Iliev, Theja Tulabandhula, Sawyer B. Fuller, Amit Ranjan Trivedi:
Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory. 68-80 - Ning-Chi Huang, Chao-Wei Cheng, Kai-Chiang Wu:
Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs. 81-94 - Weidong Zhang, Zhenxing Dong, Yan Zhu:
EddySuperblock: Improving NAND Flash Efficiency and Lifetime by Endurance-Driven Dynamic Superblock Management. 95-107 - Sumit Walia, Bachu Varun Tej, Arpita Kabra, Joydeep Kumar Devnath, Joycee Mekie:
Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation. 108-111 - Moslem Heidarpur, Mitra Mirhassani:
Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation". 112
Volume 30, Number 2, February 2022
- Lianxi Liu, Yaling Ji, Xufeng Liao, Zhenghe Qin, Hongzhi Liang:
A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity. 113-122 - Liang Fang, Xianshan Wen, Tao Fu, Guanhua Wang, Sandeep Miryala, Tiehui Ted Liu, Ping Gui:
A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoMS in 65-nm CMOS. 123-133 - Zhong Zhang, Qi Yu, Qihui Zhang, Jing Li, Kejun Wu, Ning Ning:
A Code-Recombination Algorithm-Based ADC With Feature Extraction for WBSN Applications. 134-142 - Jahyun Koo, Jae-Yoon Sim:
Low-Noise Distributed RC Oscillator. 143-152 - Shinya Kajiyama, Yutaka Igarashi, Toru Yazaki, Yusaku Katsube, Takuma Nishimoto, Tatsuo Nakagawa, Yohei Nakamura, Yoshihiro Hayashi, Takuya Kaneko, Hiroki Ishikuro, Taizo Yamawaki:
T/R Switch Composed of Three HV-MOSFETs With 12.1-μW Consumption That Enables Per-Channel Self-Loopback AC Tests and -18.1-dB Switching Noise Suppression for 3-D Ultrasound Imaging With 3072-Ch Transceiver. 153-165 - Rohit B. Chaurasiya, Rahul Shrestha:
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network. 166-176 - Pietro Nannipieri, Stefano Di Matteo, Luca Baldanzi, Luca Crocetti, Luca Zulberti, Sergio Saponara, Luca Fanucci:
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative. 177-186 - Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi:
Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks on Arbiter-PUFs and Their Derivatives. 187-200 - Dionysios Filippas, Nikolaos Margomenos, Nikolaos Mitianoudis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Low-Cost Online Convolution Checksum Checker. 201-212 - Wei Mao, Kai Li, Quan Cheng, Liuyao Dai, Boyu Li, Xinang Xie, He Li, Longyang Lin, Hao Yu:
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing. 213-226 - Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk:
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. 227-237 - Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak, Rui Paulo Martins:
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM. 238-242 - Botao Xiong, Yukun Li, Sicun Li, Sheng Fan, Yuchun Chang:
Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter. 243-247 - Yosef Lempel, Rinat Breuer, Joseph Shor:
A 700-μm², Ring-Oscillator-Based Thermal Sensor in 16-nm FinFET. 248-252
Volume 30, Number 3, March 2022
- Nakisa Shams, Frederic Nabki:
Analysis and Comparison of Low-Power 6-GHz N-Path-Filter-Based Harmonic Selection RF Receiver Front-End Architectures. 253-266 - Jinhai Xiao, Ning Liang, Bingwen Chen, Maliang Liu:
An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping. 267-276 - Mahesh Kumar Adimulam, M. B. Srinivas:
A 12-bit, 1.1-GS/s, Low-Power Flash ADC. 277-290 - Zhen Gao, Han Zhang, Yi Yao, Jiajun Xiao, Shulin Zeng, Guangjun Ge, Yu Wang, Anees Ullah, Pedro Reviriego:
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning. 291-302 - Kasem Khalil, Omar Eldash, Ashok Kumar, Magdy A. Bayoumi:
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator. 303-314 - Hamidreza Esmaeili Taheri, Mitra Mirhassani:
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach. 315-324 - Shuo Yang, Tamzidul Hoque, Prabuddha Chakraborty, Swarup Bhunia:
Golden-Free Hardware Trojan Detection Using Self-Referencing. 325-338 - Divya Praneetha Ravipati, Rajesh Kedia, Victor M. van Santen, Jörg Henkel, Preeti Ranjan Panda, Hussam Amrouch:
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. 339-352
Volume 30, Number 4, April 2022
- Leilei Jin, Wenjie Fu, Ming Ling, Longxing Shi:
A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming. 353-364 - Sandeep Krishna Thirumala, Arnab Raha, Sumeet Kumar Gupta, Vijay Raghunathan:
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors. 365-378 - Yewei Zhang, Kejie Huang, Rui Xiao, Bo Wang, Yanfeng Xu, Jicong Fan, Haibin Shen:
An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping. 379-391 - Mengyun Liu, Krishnendu Chakrabarty:
Online Fault Detection in ReRAM-Based Computing Systems for Inferencing. 392-405 - Laxmeesha Somappa, Maryam Shojaei Baghini:
Continuous-Time Hybrid ΔΣ Modulators for Sub-μW Power Multichannel Biomedical Applications. 406-417 - Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Huawei Li, Xiaowei Li:
Taming Process Variations in CNFET for Efficient Last-Level Cache Design. 418-431 - Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial:
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. 432-439 - Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial:
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization. 440-448 - Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia, Sandip Ray:
SoCCom: Automated Synthesis of System-on-Chip Architectures. 449-462 - Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro:
Optimization of Gate Voltage in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. 463-473 - Rui Yao, Yinhua Zhao, Yongchuan Yu, Yihe Zhao, Xueyan Zhong:
Fast Search and Efficient Placement Algorithm for Reconfigurable Tasks on Modern Heterogeneous FPGAs. 474-487 - Mesala M. Sravani, Ananiah Durai Sundararajan:
On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication. 488-501 - Weixiong Jiang, Heng Yu, Hongtu Zhang, Yuhao Shu, Rui Li, Jian Chen, Yajun Ha:
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA. 502-514 - Hassan Salmani:
Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist. 515-525 - Eslam Elmitwalli, Kai Ni, Selçuk Köse:
Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF. 526-538 - Abdullah Ibn Abbas, Glenn E. R. Cowan:
A Receiver Front-End for VCSEL-Based Optical Links With 49 UI Turn-On Time. 539-543 - Fei Lyu, Yan Xia, Yuheng Chen, Yanxu Wang, Yuanyong Luo, Yu Wang:
High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers. 544-548 - Erfan Bank Tavakoli, Amir Beygi, Xuebin Yao:
RPkNN: An OpenCL-Based FPGA Implementation of the Dimensionality-Reduced kNN Algorithm Using Random Projection. 549-552
Volume 30, Number 5, May 2022
- Dayane Reis, Haoran Geng, Michael T. Niemier, Xiaobo Sharon Hu:
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption. 553-565 - Yue Zhao, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Zhongzhen Tong, Junning Chen:
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing. 566-578 - Dai Li, Akhil Reddy Pakala, Kaiyuan Yang:
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator. 579-588 - Hayssam El-Razouk:
Input-Latency Free Versatile Bit-Serial GF(2m) Polynomial Basis Multiplication. 589-602 - Madhan Thirumoorthi, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid:
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic. 603-614 - Sandeep Goyal, Ganpat Anant Parulekar, Shalabh Gupta:
A True Full-Duplex IO (TFD-IO) With Background SI Cancellation for High-Density Interfaces. 615-624 - Yulang Feng, Hao Deng, Qingjun Fan, Yuxuan Tang, Phaneendra Bikkina, Esko Mikkola, Jinghong Chen:
A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation. 625-633 - Yan-Ting Chen, Pen-Jui Peng, Hung-Wen Lin:
A 12-14.5-GHz 10.2-mW -249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS. 634-643 - Qihui Zhang, Ning Ning, Zhong Zhang, Jing Li, Kejun Wu, Qi Yu:
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator. 644-655 - Yuhao Chen, Hongge Li:
Stochastic Computing Using Amplitude and Frequency Encoding. 656-660 - Hesheng Lin, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne:
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. 661-665 - Shatadal Chatterjee, Sounak Roy:
A Self-Calibration Method of a Pipeline ADC Based on Dynamic Capacitance Allotment. 666-670 - Biswabandhu Jana, Pallab Kumar Nath:
A Single-Chip Solution for Diagnosing Peripheral Arterial Disease. 671-675 - Yuting Chen, Yuxuan Nie, Hailong Jiao:
An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold Digital Circuits. 676-680
Volume 30, Number 6, June 2022
- Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross:
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND. 681-693 - Yiming Yu, Dong Chen, Xiaoning Zhang, Chenxi Zhao, Huihua Liu, Yunqiu Wu, Wen-Yan Yin, Kai Kang:
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology. 694-705 - Yao Li, Bo Zhou, Fuyuan Zhao, Yujie Liu, Yeran Jin:
A 1.15-mW Low-Power Low-Complexity Reconfigurable FM-UWB Transmitter. 706-719 - Naina Singhal, S. M. Rezaul Hasan:
A 25-30-GHz RMS Error-Minimized 360° Continuous Analog Phase Shifter Using Closed-Loop Self-Tuning I/Q Generator. 720-731 - Xiaolong Liu, Howard C. Luong:
Analysis and Design of Magnetically Tuned W -Band Oscillators. 732-743 - Ningcheng Gaoding, Jean-François Bousquet:
A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active-Passive Integrators With a Resistance Feedback DAC. 744-754 - Souvik Kundu, Priyanka B. Ganganaik, Jeffry Louis, Hemanth Chalamalasetty, BVVSN Prabhakar Rao:
Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture. 755-768 - Jian Chen, Wenfeng Zhao, Yuqi Wang, Yuhao Shu, Weixiong Jiang, Yajun Ha:
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations. 769-780 - Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang:
ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM. 781-793 - Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Efficient Error Detection Architectures for Postquantum Signature Falcon's Sampler and KEM SABER. 794-802 - Ziying Ni, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu:
A High-Performance SIKE Hardware Accelerator. 803-815 - Kuo-Wei Chang, Hsu-Tung Shih, Tian-Sheuan Chang, Shang-Hong Tsai, Chih-Chyau Yang, Chien-Ming Wu, Chun-Ming Huang:
A Real-Time 1280 × 720 Object Detection Chip With 585 MB/s Memory Traffic. 816-825 - Sina Ghaffari, David W. Capson, Kin Fun Li:
A Fully Pipelined FPGA Architecture for Multiscale BRISK Descriptors With a Novel Hardware-Aware Sampling Pattern. 826-839 - Youngwoo Ji, Jae-Yoon Sim:
A 20.5-nW Resistor-Less Bandgap Voltage Reference With Self-Biased Compensation for Process Variations. 840-843 - Mohamadreza Zolfagharinejad, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
Posit Process Element for Using in Energy-Efficient DNN Accelerators. 844-848
Volume 30, Number 7, July 2022
- Yuyang Li, Yawen Wu, Xincheng Zhang, Jingtong Hu, Inhee Lee:
Energy-Aware Adaptive Multi-Exit Neural Network Inference Implementation for a Millimeter-Scale Sensing System. 849-859 - Paria Darbani, Nezam Rohbani, Hakem Beitollahi, Pejman Lotfi-Kamran:
RASHT: A Partially Reconfigurable Architecture for Efficient Implementation of CNNs. 860-868 - Khaled Alhaj Ali, Amer Baghdadi, Elsa Dupraz, Mathieu Léonardon, Mostafa Rizk, Jean-Philippe Diguet:
MOL-Based In-Memory Computing of Binary Neural Networks. 869-880 - Kashif Inayat, Jaeyong Chung:
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration. 881-892 - Daney Alex, Vinay Chakravarthi Gogineni, Subrahmanyam Mula, Stefan Werner:
Novel VLSI Architecture for Fractional-Order Correntropy Adaptive Filtering Algorithm. 893-904 - Yao-Hung Tsai, Shen-Iuan Liu:
A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS. 905-914 - Dong-Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Jae-Soub Han, Keun-Yong Chung, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek:
A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier. 915-925 - Hammond Pearce, Virinchi Roy Surabhi, Prashanth Krishnamurthy, Joshua Trujillo, Ramesh Karri, Farshad Khorrami:
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks. 926-937 - Kerem Arikan, Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Salvatore Pontarelli, Giuseppe Bianchi, Oguz Ergin, Marco Ottavi:
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. 938-951 - Subodha Charles, Vincent Bindschaedler, Prabhat Mishra:
Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures. 952-965 - Feng Qiu, Haoshen Zhu, Wenquan Che, Quan Xue:
A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain. 966-974 - Shuo-Wen Chang, Yu-Teng Nien, Yu-Pang Hu, Kai-Chiang Wu, Chi Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, Mango C.-T. Chao:
Test Methodology for Defect-Based Bridge Faults. 975-988 - Fengjuan Wang, Kai Zhang, Xiangkun Yin, Ningmei Yu, Yuan Yang:
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application. 989-992
Volume 30, Number 8, August 2022
- Yang Su, Bai-Long Yang, Chen Yang, Zepeng Yang, Yi-Wei Liu:
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication. 993-1006 - Dongdong Xu, Xiang Wang, Yuanchao Hao, Zhun Zhang, Qiang Hao, Zhiyu Zhou:
A More Accurate and Robust Binary Ring-LWE Decryption Scheme and Its Hardware Implementation for IoT Devices. 1007-1019 - Rahul Sharma, Rahul Shrestha, Satinder K. Sharma:
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method. 1020-1033 - Jinming Lu, Jian Huang, Zhongfeng Wang:
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration. 1034-1046 - Yichuan Bai, Mingzhe Jiang, Qingyu Zhu, Xiaoliang Chen, Yuan Du, Li Du, Zhongfeng Wang:
An Efficient High-Throughput Structured-Light Depth Engine. 1047-1058 - Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin:
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. 1059-1072 - Naveen Kumar Macha, Bhavana Tejaswini Repalle, Md Arif Iqbal, Mostafizur Rahman:
Crosstalk-Computing-Based Gate-Level Reconfigurable Circuits. 1073-1083 - Baver Ozceylan, Boudewijn R. Haverkort, Maurits de Graaf, Marco E. T. Gerards:
Minimizing the Maximum Processor Temperature by Temperature-Aware Scheduling of Real-Time Tasks. 1084-1097 - Fereshteh Kalantari, Hossein Hosseini-Nejad, Amir M. Sodagar:
Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems. 1098-1106 - Wei Xiong, Gang Dong, Yang Wang, Zhangming Zhu, Yintang Yang:
3-D Compact Marchand Balun Design Based on Through-Silicon via Technology for Monolithic and 3-D Integration. 1107-1118 - Yu-Hsuan Lee, Yu-Hsing Chiu, Szu-Hsuan Lai, Wen-Yu Chiou, Yue-Fang Kuo:
A Design of 12.8-Gpixels/s Hardware-Efficient Lossless Embedded Compression Engine for Video Coding Applications. 1119-1132
Volume 30, Number 9, September 2022
- Xuecheng Wang, Yahao Song, Fengfan Hou, Milin Zhang, Andrew G. Richardson, Timothy H. Lucas, Jan Van der Spiegel:
Design of a Real-Time Movement Decomposition-Based Rodent Tracker and Behavioral Analyzer Based on FPGA. 1133-1143 - Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. 1144-1157 - Tengfei Wang, Chi Zhang, Pei Cao, Dawu Gu:
Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform. 1158-1171