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2010 – 2019
- 2013
[j2]Lars Sundström
, Staffan Ek, Jim Svensson, Martin Anderson, Roland Strandberg, Fenghao Mu, Imad ud Din, Thomas Olsson, Leif R. Wilhelmsson, Daniel Eckerbert:
Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS. IEEE J. Solid State Circuits 48(7): 1659-1668 (2013)- [c10]Lars Sundström, Martin Anderson, Roland Strandberg, Staffan Ek, Jim Svensson, Fenghao Mu, Thomas Olsson, Imad ud Din, Leif R. Wilhelmsson, Daniel Eckerbert, Sven Mattisson:
A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation. ISSCC 2013: 336-337 - 2012
- [c9]Lars Sundström, Staffan Ek, Jim Svensson, Martin Anderson, Roland Strandberg, Fenghao Mu, Imad ud Din, Thomas Olsson, Leif R. Wilhelmsson, Daniel Eckerbert:
Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS. ESSCIRC 2012: 357-360 - [c8]Martin Anderson, Roland Strandberg, Staffan Ek, Leif R. Wilhelmsson, Lars Sundström, Mattias Andersson, Imad ud Din, Jim Svensson, Thomas Olsson, Daniel Eckerbert:
A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS. ESSCIRC 2012: 470-473
2000 – 2009
- 2006
- [j1]Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert:
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 370-379 (2006) - 2004
- [c7]Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson:
A power cut-off technique for gate leakage suppression [CMOS logic circuits]. ESSCIRC 2004: 171-174 - 2003
- [c6]Daniel Eckerbert, Per Larsson-Edefors:
A deep submicron power estimation methodology adaptable to variations between power characterization and estimation. ASP-DAC 2003: 716-719 - [c5]Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors:
A Mixed-Mode Delay-Locked-Loop Architecture. ICCD 2003: 261-263 - [c4]Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson:
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ISVLSI 2003: 225-230 - 2001
- [c3]Daniel Eckerbert, Per Larsson-Edefors:
Interconnect-Driven Short-Circuit Power Modeling. DSD 2001: 414-421 - [c2]Daniel Eckerbert, Per Larsson-Edefors:
Cycle-true leakage current modeling for CMOS gates. ISCAS (5) 2001: 507-510 - 2000
- [c1]Daniel Eckerbert, Henrik Eriksson, Per Larsson-Edefors, Anders Edman:
An interconnect-driven design of a DFT processor. ISCAS 2000: 569-572
Coauthor Index
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