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Franck Arnaud
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2020 – today
- 2024
- [c13]R. Berthelon, Olivier Weber, F. Ibars, B. Revel, C. Borowiak, J. C. Grenier, B. Dumont, S. Desmoulins, P. O. Sassoulas, P. Ferreira, S. Chouteau, S. Niel, Rossella Ranica, R. Gonella, Franck Arnaud:
Unlimited Bi-directional Back-Bias in FD-SOI Technology With New Dual Isolation Integration. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c12]Antonino Conte, Francesco Tomaiuolo, Marco Ruta, Andrea Redaelli, Franck Arnaud, Thomas Jouanneau, Christian Boccaccio, Olivier Weber:
An 18nm ePCM with BJT selector NVM design for advanced microcontroller applications. IMW 2023: 1-4 - [i1]Joao Henrique Quintino Palhares, Yann Beilliard, Jury Sandrini, Franck Arnaud, Kevin Garello, Guillaume Prenat, Lorena Anghel, Fabien Alibart, Dominique Drouin, Philippe Galy:
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. CoRR abs/2305.16187 (2023) - 2021
- [c11]Joël Hartmann, Paolo Cappelletti, Nitin Chawla, Franck Arnaud, Andreia Cathelin:
Artificial Intelligence: Why moving it to the Edge? ESSCIRC 2021: 1-6 - [c10]Joël Hartmann, Paolo Cappelletti, Nitin Chawla, Franck Arnaud, Andreia Cathelin:
Artificial Intelligence: Why moving it to the Edge? ESSDERC 2021: 1-6 - [c9]Andrea Redaelli, Anna Gandolfo, Giulia Samanni, Enrico Gomiero, Elisa Petroni, Luca Scotti, Andrea Lippiello, Paolo Mattavelli, J. Jasse, D. Codegoni, A. Serafini, Rossella Ranica, Christian Boccaccio, Jury Sandrini, R. Berthelon, J. C. Grenier, Olivier Weber, David Turgis, A. Valery, S. Del Medico, V. Caubet, J. P. Reynard, Didier Dutartre, L. Favennec, Antonino Conte, Fabio Disegni, M. De Tomasi, A. Ventre, Matteo Baldo, Daniele Ielmini, Alfonso Maurelli, P. Ferreira, Franck Arnaud, F. Piazza, Paolo Cappelletti, Roberto Annunziata, R. Gonella:
Improving Ge-rich GST ePCM reliability through BEOL engineering. ESSDERC 2021: 231-234 - [c8]Fabio Disegni, A. Ventre, A. Molgora, Paolo Cappelletti, R. Badalamenti, P. Ferreira, G. Castagna, Andreia Cathelin, Anna Gandolfo, Andrea Redaelli, D. Manfrè, Alfonso Maurelli, C. Torti, F. Piazza, M. Carfì, Franck Arnaud, M. Perroni, M. Caruso, S. Pezzini, Roberto Annunziata, G. Piazza, Olivier Weber, M. Peri:
16MB High Density Embedded PCM macrocell for automotive-grade microcontroller in 28nm FD-SOI, featuring extension to 24MB for Over-The-Air software update. VLSI Circuits 2021: 1-2
2010 – 2019
- 2019
- [c7]Franck Arnaud, Sébastien Haendler, Sylvain Clerc, Rossella Ranica, Anna Gandolfo, Olivier Weber:
28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications. ESSCIRC 2019: 7-10 - [c6]Franck Arnaud, Sébastien Haendler, Sylvain Clerc, Rossella Ranica, Anna Gandolfo, Olivier Weber:
28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications. ESSDERC 2019: 7-10 - [c5]Fabio Disegni, Roberto Annunziata, A. Molgora, G. Campardo, Paolo Cappelletti, P. Zuliani, P. Ferreira, A. Ventre, G. Castagna, Andreia Cathelin, Anna Gandolfo, F. Goller, S. Malhi, D. Manfrè, Alfonso Maurelli, C. Torti, Franck Arnaud, M. Carfì, M. Perroni, M. Caruso, S. Pezzini, G. Piazza, Olivier Weber, M. Peri:
Embedded PCM macro for automotive-grade microcontroller in 28nm FD-SOI. VLSI Circuits 2019: 204- - 2016
- [c4]Rossella Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, Daniel Noblet, Damien Croain, Fabien Giner, Sylvie Naudet, P. Mergault, S. Ibars, A. Villaret, Maryline Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud:
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. VLSI Circuits 2016: 1-2 - 2014
- [j2]David Jacquet, Frederic Hasbani, Philippe Flatresse, Robin Wilson, Franck Arnaud, Giorgio Cesana, Thierry Di Gilio, Christophe Lecocq, Tanmoy Roy, Amit Chhabra, Chiranjeev Grover, Olivier Minez, Jacky Uginet, Guy Durieu, Cyril Adobati, Davide Casalotto, Frederic Nyer, Patrick Menut, Andreia Cathelin, Indavong Vongsavady, Philippe Magarshack:
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. IEEE J. Solid State Circuits 49(4): 812-826 (2014) - [c3]François Andrieu, Mikaël Cassé, E. Baylac, P. Perreau, O. Nier, Denis Rideau, R. Berthelon, Franck Pourchon, A. Pofelski, Barbara De Salvo, C. Gallon, Vincent Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, Vincent Barral, Rossella Ranica, Nicolas Planes, Walter Schwarzenbach, E. Richard, Emmanuel Josse, Olivier Weber, Franck Arnaud, Maud Vinet, Olivier Faynot, Michel Haond:
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. ESSDERC 2014: 106-109 - 2013
- [c2]Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard:
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. ISSCC 2013: 424-425 - 2012
- [c1]Christoforos G. Theodorou, Eleftherios G. Ioannidis, Sébastien Haendler, Nicolas Planes, Franck Arnaud, Jalal Jomaah, Charalambos A. Dimitriadis, Gérard Ghibaudo:
Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs. ESSDERC 2012: 334-337 - 2011
- [j1]Franck Arnaud, L. Pinzelli, C. Gallon, M. Rafik, P. Mora, Frédéric Boeuf:
Challenges and opportunity in performance, variability and reliability in sub-45 nm CMOS technologies. Microelectron. Reliab. 51(9-11): 1508-1514 (2011)
Coauthor Index
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