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ORCIDChao-Tsung Huang
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- affiliation: National Tsing Hua University, Taiwan
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2020 – today
- 2023
[c39]Hao-Jiun Tu, Yu-Feng Ou, Yong-Tai Chen, Chao-Tsung Huang:
A Biased Mixed-Precision Convolution Engine for Hardware-Efficient Computational Imaging CNN. APSIPA ASC 2023: 1365-1371- [c38]Kai-Ping Lin, Jia-Han Liu, Jyun-Yi Wu, Hong-Chuan Liao, Chao-Tsung Huang:
VISTA: A 704mW 4K-UHD CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration. ISSCC 2023: 48-49 - 2022
- [j19]Ching-Te Chiu
, Yu-Chun Ding, Wei-Chen Lin, Wei-Jyun Chen, Shu-Yun Wu, Chao-Tsung Huang, Chun-Yeh Lin, Chia-Yu Chang, Meng-Jui Lee, Shimazu Tatsunori, Tsung Chen, Fan-Yi Lin, Yuan-Hao Huang:
Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4847-4859 (2022) - [c37]Yong-Tai Chen, Yu-Feng Ou, Chao-Tsung Huang:
A Winograd-Based Highly-Parallel Convolution Engine for 8-bit CNN Acceleration. AICAS 2022: 395-398 - [c36]Yu-Chun Ding, Kai-Pin Lin, Chi-Wen Weng, Li-Wei Wang, Huan-Ching Wang, Chun-Yeh Lin, Yong-Tai Chen, Chao-Tsung Huang:
A 4.6-8.3 TOPS/W 1.2-4.9 TOPS CNN-based Computational Imaging Processor with Overlapped Stripe Inference Achieving 4K Ultra-HD 30fps. ESSCIRC 2022: 81-84 - [c35]Li-Qun Weng, Li-De Chen, Hao-Chien Cheng, An-You Zheng, Kai-Ping Lin, Chao-Tsung Huang:
A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display. ISSCC 2022: 1-3 - 2021
- [j18]Ching-Chen Wang, Yu-Chun Ding, Ching-Te Chiu, Chao-Tsung Huang, Yen-Yu Cheng, Shih-Yi Sun, Chih-Han Cheng, Hsueh-Kai Kuo:
Real-Time Block-Based Embedded CNN for Gesture Classification on an FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4182-4193 (2021) - [c34]Chi-Wen Weng, Chao-Tsung Huang:
A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration. AICAS 2021: 1-4 - [c33]Chao-Tsung Huang:
RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging. ISCA 2021: 1096-1109 - [c32]Hsiu-Pin Hsu, Chao-Tsung Huang:
Globally Assisted Instance Normalization for Bandwidth-Efficient Neural Style Transfer. SiPS 2021: 58-63 - [i3]Chao-Tsung Huang:
RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging. CoRR abs/2104.09056 (2021) - 2020
- [c31]Ching-Chen Wang, Ching-Te Chiu, Chao-Tsung Huang, Yu-Chun Ding, Li-Wei Wang:
Fast and Accurate Embedded DCNN for Rgb-D Based Sign Language Recognition. ICASSP 2020: 1568-1572 - [c30]Chao-Tsung Huang:
Ernet Family: Hardware-Oriented Cnn Models For Computational Imaging Using Block-Based Inference. ICASSP 2020: 1643-1647 - [c29]Shih-Yao Huang, Wei-Chih Chen, Chao-Tsung Huang:
FIR Filter Design and Implementation for Phase-Based Processing. ICASSP 2020: 1748-1752
2010 – 2019
- 2019
- [j17]Chao-Tsung Huang:
Empirical Bayesian Light-Field Stereo Matching by Robust Pseudo Random Field Modeling. IEEE Trans. Pattern Anal. Mach. Intell. 41(3): 552-565 (2019) - [c28]Han-Chih Huang, Yu-Chih Wang, Wei-Chih Chen, Ping-Yen Lin, Chao-Tsung Huang:
System and VLSI Implementation of Phase-based View Synthesis. ICASSP 2019: 1428-1432 - [c27]Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang, Li-De Chen:
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference. MICRO 2019: 182-195 - [c26]Po-Han Chen, Shu-Wen Yang, Shih-Yao Huang, Li-De Chen, Chao-Tsung Huang:
A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications. VLSI Circuits 2019: 154- - [i2]Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang, Li-De Chen:
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference. CoRR abs/1910.05680 (2019) - [i1]Chao-Tsung Huang:
ERNet Family: Hardware-Oriented CNN Models for Computational Imaging Using Block-Based Inference. CoRR abs/1910.05787 (2019) - 2018
- [c25]Li-De Chen, Yu-Ta Lu, Yu-Ling Hsiao, Bo-Hsiang Yang, Wei-Chi Chen, Chao-Tsung Huang:
A 95pJ/label Wide-Range Depth-Estimation Processor for Full-HD Light-Field Applications on FPGA. A-SSCC 2018: 261-262 - [c24]Bo-Hsiang Yang, Li-De Chen, Chao-Tsung Huang:
A 320M Pixel/S Vlsi Architecture Design of Weighted Mode Filter for 4K Ultra-Hd Depth Upsampling. ICASSP 2018: 1125-1129 - 2017
- [j16]Chao-Tsung Huang, Yu-Wen Wang, Li-Ren Huang, Jui Chin, Liang-Gee Chen:
Fast Physically Correct Refocusing for Sparse Light Fields Using Block-Based Multi-Rate View Interpolation. IEEE Trans. Image Process. 26(2): 603-618 (2017) - [c23]Chao-Tsung Huang:
Robust Pseudo Random Fields for Light-Field Stereo Matching. ICCV 2017: 11-19 - 2016
- [j15]Chao-Tsung Huang:
Fast Distribution Fitting for Parameter Estimation of Range-Weighted Neighborhood Filters. IEEE Signal Process. Lett. 23(3): 331-335 (2016) - [c22]Li-Ren Huang, Yu-Wen Wang, Chao-Tsung Huang:
Fast realistic block-based refocusing for sparse light fields. ISCAS 2016: 998-1001 - [c21]Li-De Chen, Yu-Ling Hsiao, Chao-Tsung Huang:
VLSI architecture design of weighted mode filter for Full-HD depth map upsampling at 30fps. ISCAS 2016: 1578-1581 - 2015
- [j14]Chao-Tsung Huang:
Bayesian Inference for Neighborhood Filters With Application in Denoising. IEEE Trans. Image Process. 24(11): 4299-4311 (2015) - [c20]Chao-Tsung Huang:
Bayesian inference for neighborhood filters with application in denoising. CVPR 2015: 1657-1665 - [c19]Chao-Tsung Huang, Jui Chin, Hong-Hui Chen, Yu-Wen Wang, Liang-Gee Chen:
Fast realistic refocusing for sparse light fields. ICASSP 2015: 1176-1180 - [c18]Li-De Chen, Jo-Jiun Yu, Wei-Han Cheng, Chao-Tsung Huang:
Sub-pixel disparity estimation in continuous space. ICCE-TW 2015: 114-115 - [c17]Hong-Hui Chen, Chao-Tsung Huang, Sih-Sian Wu, Chia-Liang Hung, Tsung-Chuan Ma, Liang-Gee Chen:
23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications. ISSCC 2015: 1-3 - 2014
- [j13]Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications. IEEE J. Solid State Circuits 49(1): 61-72 (2014) - [j12]Chao-Tsung Huang, Mehul Tikekar, Anantha P. Chandrakasan:
Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1515-1525 (2014) - [c16]Mehul Tikekar, Chao-Tsung Huang, Vivienne Sze, Anantha P. Chandrakasan:
Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization. ICIP 2014: 2100-2104 - [p1]Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
Decoder Hardware Architecture for HEVC. High Efficiency Video Coding 2014: 303-341 - 2013
- [c15]Chao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications. ISSCC 2013: 162-163 - [c14]Chao-Tsung Huang, Chiraag Juvekar, Mehul Tikekar, Anantha P. Chandrakasan:
HEVC interpolation filter architecture for quad full HD decoding. VCIP 2013: 1-5
2000 – 2009
- 2007
- [j11]Chih-Chi Cheng, Chao-Tsung Huang, Ching-Yeh Chen, Chung-Jr Lian, Liang-Gee Chen:
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform. IEEE Trans. Circuits Syst. Video Technol. 17(7): 814-822 (2007) - 2006
- [j10]Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Liang-Gee Chen:
Level C+ data reuse scheme for motion estimation with corresponding coding orders. IEEE Trans. Circuits Syst. Video Technol. 16(4): 553-558 (2006) - [j9]Hung-Chi Fang, Yu-Wei Chang, Tu-Chih Wang, Chao-Tsung Huang, Liang-Gee Chen:
High-Performance JPEG 2000 Encoder With Rate-Distortion Optimization. IEEE Trans. Multim. 8(4): 645-653 (2006) - [j8]Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Shao-Yi Chien, Liang-Gee Chen:
System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering. IEEE Trans. Signal Process. 54(10): 4004-4014 (2006) - [c13]Chih-Chi Cheng, Chao-Tsung Huang, Jing-Ying Chang, Liang-Gee Chen:
Line Buffer Wordlength Analysis for Line-Based 2-D DWT. ICASSP (3) 2006: 924-927 - 2005
- [j7]Po-Chih Tseng, Yung-Chi Chang, Yu-Wen Huang, Hung-Chi Fang, Chao-Tsung Huang, Liang-Gee Chen:
Advances in Hardware Architectures for Image and Video Coding - A Survey. Proc. IEEE 93(1): 184-197 (2005) - [j6]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method. IEEE Trans. Circuits Syst. Video Technol. 15(7): 910-920 (2005) - [j5]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform. IEEE Trans. Signal Process. 53(4): 1575-1586 (2005) - [j4]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters. J. VLSI Signal Process. 40(2): 175-188 (2005) - [j3]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization. J. VLSI Signal Process. 40(3): 343-353 (2005) - [j2]Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen:
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems. J. VLSI Signal Process. 41(1): 35-47 (2005) - [c12]Chao-Tsung Huang, Ching-Yeh Chen, Yi-Hau Chen, Liang-Gee Chen:
Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications]. ICASSP (5) 2005: 93-96 - [c11]Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Chung-Jr Lian, Liang-Gee Chen:
System analysis of VLSI architecture for motion-compensated temporal filtering. ICIP (3) 2005: 992-995 - [c10]Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen:
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. ISCAS (2) 2005: 1790-1793 - [c9]Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen:
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT. ISCAS (5) 2005: 5190-5193 - 2004
- [j1]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. IEEE Trans. Signal Process. 52(4): 1080-1089 (2004) - [c8]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
Memory analysis and architecture for two-dimensional discrete wavelet transform. ICASSP (5) 2004: 13-16 - [c7]Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen:
Reconfigurable discrete cosine transform processor for object-based video signal processing. ISCAS (2) 2004: 353-356 - [c6]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
B-spline factorization-based architecture for inverse discrete wavelet transform. ISCAS (2) 2004: 829-832 - 2003
- [c5]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank. ICIP (2) 2003: 571-574 - 2002
- [c4]Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen:
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method. APCCAS (1) 2002: 363-366 - [c3]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. APCCAS (1) 2002: 383-388 - [c2]Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. ISCAS (5) 2002: 565-568 - [c1]Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen:
VLSI implementation of shape-adaptive discrete wavelet transform. VCIP 2002: 655-666
Coauthor Index
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