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2020 – today
- 2024
[c11]Florian Cacho, P. Cathelin, Joycelyn Hai, S. Bouvot, J. Nowakowski, M. Martinez, R. Debroucke, S. Jean, R. Paulin, J. Antonijevic, X. Federspiel, Nicolas Planes, Giuseppe Papotto, Alessandro Parisi, Alessandro Finocchiaro, Andrea Cavarra, Alessandro Castorina, Claudio Nocera, Giuseppe Palmisano:
Robustness Assessment Through 77GHz Operating Life Test of Power Amplifier for Radar Applications in 28nm FD-SOI CMOS. IRPS 2024: 4
2010 – 2019
- 2019
- [c10]Lucas Nyssens, Arka Halder
, Babak Kazemi Esfeh, Nicolas Planes, Michel Haond, Denis Flandre, Jean-Pierre Raskin, Valeriya Kilchytska:
Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures. ESSDERC 2019: 162-165 - 2017
- [c9]B. Kazemi Esfeh, Valeria Kilchytska, Bertrand Parvais, Nicolas Planes, M. Haond, Denis Flandre, Jean-Pierre Raskin:
Back-gate bias effect on UTBB-FDSOI non-linearity performance. ESSDERC 2017: 148-151 - 2016
- [c8]Rossella Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, Daniel Noblet, Damien Croain, Fabien Giner, Sylvie Naudet, P. Mergault, S. Ibars, A. Villaret, Maryline Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud:
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. VLSI Circuits 2016: 1-2 - 2015
- [c7]Christoforos G. Theodorou, Eleftherios G. Ioannidis, Sébastien Haendler, Nicolas Planes, Emmanuel Josse, Charalambos A. Dimitriadis, Gérard Ghibaudo:
New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs. IRPS 2015: 1 - 2014
- [c6]François Andrieu, Mikaël Cassé, E. Baylac, P. Perreau, O. Nier, Denis Rideau, R. Berthelon, Franck Pourchon, A. Pofelski, Barbara De Salvo, C. Gallon, Vincent Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, Vincent Barral, Rossella Ranica, Nicolas Planes, Walter Schwarzenbach, E. Richard, Emmanuel Josse, Olivier Weber, Franck Arnaud, Maud Vinet, Olivier Faynot, Michel Haond:
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. ESSDERC 2014: 106-109 - [c5]Eleftherios G. Ioannidis, Sébastien Haendler, Christoforos G. Theodorou, Nicolas Planes, Charalabos A. Dimitriadis, Gérard Ghibaudo:
Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs. ESSDERC 2014: 214-217 - [c4]Sergej Makovejev, Babak Kazemi Esfeh, Jean-Pierre Raskin, Valeria Kilchytska, Denis Flandre, Vincent Barral, Nicolas Planes, Michel Haond:
Variability of UTBB MOSFET analog figures of merit in wide frequency range. ESSDERC 2014: 222-225 - 2013
- [c3]Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard:
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. ISSCC 2013: 424-425 - 2012
- [c2]Christoforos G. Theodorou, Eleftherios G. Ioannidis, Sébastien Haendler, Nicolas Planes, Franck Arnaud, Jalal Jomaah, Charalambos A. Dimitriadis, Gérard Ghibaudo:
Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs. ESSDERC 2012: 334-337
2000 – 2009
- 2002
- [c1]Thierry Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, David Roy, B. Borot, Nicolas Planes, Sylvie Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond:
Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC). MTDT 2002: 157-162
Coauthor Index
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