Stop the war!Остановите войну!
for scientists:
Google
Google Scholar
Semantic Scholar
IA Scholar
CiteSeerX
ORCIDJae-sun Seo
Jae-Sun Seo
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2022
[j39]Jian Meng
, Wonbo Shim, Li Yang, Injune Yeo, Deliang Fan, Shimeng Yu, Jae-sun Seo:
Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference. IEEE Micro 42(1): 89-98 (2022)- [c83]Fan Zhang, Li Yang, Jian Meng, Yu Kevin Cao, Jae-sun Seo, Deliang Fan:
XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption. ASP-DAC 2022: 610-615 - [c82]Jian Meng, Injune Yeo, Wonbo Shim, Li Yang, Deliang Fan, Shimeng Yu, Jae-Sun Seo:
Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference. IRPS 2022: 3 - 2021
- [j38]Tinoosh Mohsenin, Inna Partin-Vaisband, Houman Homayoun, Jae-Sun Seo, Xin Zhang:
Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 527-531 (2021) - [j37]Arnab Neelim Mazumder, Jian Meng, Hasib-Al Rashid, Utteja Kallakuri, Xin Zhang, Jae-Sun Seo, Tinoosh Mohsenin:
A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 532-547 (2021) - [j36]Minkyu Kim, Jae-Sun Seo:
An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access. IEEE J. Solid State Circuits 56(3): 803-813 (2021) - [j35]Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, Jae-Sun Seo:
Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1576-1580 (2021) - [j34]Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-Sun Seo, Ümit Y. Ogras, Yu Cao:
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. ACM Trans. Embed. Comput. Syst. 20(5s): 68:1-68:24 (2021) - [c81]Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-Sun Seo, Ümit Y. Ogras, Yu Cao:
System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration. ASICON 2021: 1-4 - [c80]Sai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, Jae-sun Seo:
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. DAC 2021: 559-564 - [c79]Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-Sun Seo:
Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. DATE 2021: 942-947 - [c78]Jian Meng, Shreyas Kolala Venkataramanaiah, Chuteng Zhou, Patrick Hansen, Paul N. Whatmough, Jae-sun Seo:
FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access. FPL 2021: 9-16 - [c77]Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo:
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL 2021: 76-82 - [c76]Han-Sok Suh, Jian Meng, Ty Nguyen, Shreyas K. Venkataramanaiah, Vijay Kumar, Yu Cao, Jae-sun Seo:
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA. FPT 2021: 1-9 - [c75]Wangxin He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, Jae-sun Seo:
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. IRPS 2021: 1-7 - [c74]Wonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, Shimeng Yu:
Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine. IRPS 2021: 1-4 - [c73]Vinay Joshi, Wangxin He, Jae-sun Seo, Bipin Rajendran:
Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks. ISCAS 2021: 1-5 - [c72]Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo:
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. VLSI Circuits 2021: 1-2 - [i13]Vinay Joshi, Wangxin He, Jae-sun Seo, Bipin Rajendran:
Hybrid In-memory Computing Architecture for the Training of Deep Neural Networks. CoRR abs/2102.05271 (2021) - [i12]Adnan Siraj Rakin, Li Yang, Jingtao Li, Fan Yao, Chaitali Chakrabarti, Yu Cao, Jae-sun Seo, Deliang Fan:
RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy. CoRR abs/2103.13813 (2021) - [i11]Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks. CoRR abs/2107.02358 (2021) - [i10]Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. CoRR abs/2108.08903 (2021) - 2020
- [j33]Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs. IEEE Des. Test 37(6): 79-87 (2020) - [j32]Sumit K. Mandal, Gokul Krishnan, Chaitali Chakrabarti, Jae-Sun Seo, Yu Cao, Ümit Y. Ogras:
A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 362-375 (2020) - [j31]Shihui Yin, Zhewei Jiang, Jae-Sun Seo, Mingoo Seok:
XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks. IEEE J. Solid State Circuits 55(6): 1733-1743 (2020) - [j30]Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo:
An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition. IEEE J. Solid State Circuits 55(7): 1877-1887 (2020) - [j29]Zhewei Jiang, Shihui Yin, Jae-Sun Seo, Mingoo Seok:
C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism. IEEE J. Solid State Circuits 55(7): 1888-1897 (2020) - [j28]Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, Jae-sun Seo:
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation. IEEE J. Solid State Circuits 55(10): 2680-2690 (2020) - [j27]Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Gaurav Srivastava, Chisung Bae, Sang Joon Kim, Jae-sun Seo:
ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression. IEEE Trans. Biomed. Circuits Syst. 14(2): 198-208 (2020) - [j26]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 424-437 (2020) - [j25]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Performance Modeling for CNN Inference Accelerators on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 843-856 (2020) - [j24]Shihui Yin, Zhewei Jiang, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-Sun Seo:
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 48-61 (2020) - [c71]Minkyu Kim, Jae-Sun Seo:
Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access. CICC 2020: 1-4 - [c70]Xiaocong Du, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao:
Noise-based Selection of Robust Inherited Model for Accurate Continual Learning. CVPR Workshops 2020: 983-988 - [c69]Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran:
An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. DATE 2020: 1019-1024 - [c68]Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-Sun Seo:
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. ICCAD 2020: 74:1-74:8 - [c67]Shreyas Kolala Venkataramanaiah, Xiaocong Du, Zheng Li, Shihui Yin, Yu Cao, Jae-sun Seo:
Efficient and Modularized Training on FPGA for Real-time Applications. IJCAI 2020: 5237-5239 - [c66]Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao:
Online Knowledge Acquisition with the Selective Inherited Model. IJCNN 2020: 1-7 - [c65]Deepak Kadetotad, Jian Meng, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo:
Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity. INTERSPEECH 2020: 21-25 - [c64]Wonbo Shim, Yandong Luo, Jae-sun Seo, Shimeng Yu:
Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction. IRPS 2020: 1-5 - [c63]Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Mark S. Rodder, Jae-Sun Seo, Shimeng Yu:
A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out. ISCAS 2020: 1-5 - [c62]Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, Jae-Sun Seo:
Deep Neural Network Training Accelerator Designs in ASIC and FPGA. ISOCC 2020: 21-22 - [c61]Usama Awais, Jae-sun Seo:
Regulation Control Design Techniques for Integrated Switched Capacitor Voltage Regulators. MWSCAS 2020: 186-189 - [i9]Colby R. Banbury, Vijay Janapa Reddi, Max Lam, William Fu, Amin Fazel, Jeremy Holleman, Xinyuan Huang, Robert Hurtado, David Kanter, Anton Lokhmotov, David A. Patterson, Danilo Pau, Jae-sun Seo, Jeff Sieracki, Urmish Thakker, Marian Verhelst, Poonam Yadav:
Benchmarking TinyML Systems: Challenges and Direction. CoRR abs/2003.04821 (2020)
2010 – 2019
- 2019
- [j23]Chia-Yu Chen, Boris Murmann, Jae-sun Seo, Hoi-Jun Yoo:
Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 247-252 (2019) - [j22]Jae-sun Seo, Yu Cao, Xin Li, Paul N. Whatmough:
Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning. ACM J. Emerg. Technol. Comput. Syst. 15(2): 14:1-14:2 (2019) - [j21]Jae-Sun Seo, Yu Cao, Xin Li, Paul N. Whatmough:
Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2). ACM J. Emerg. Technol. Comput. Syst. 15(4): 31:1-31:2 (2019) - [j20]Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, Chisung Bae, Sang Joon Kim, Yu Cao, Jae-sun Seo:
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring. IEEE J. Solid State Circuits 54(8): 2316-2326 (2019) - [j19]Shihui Yin, Jae-sun Seo, Yulhwa Kim, Xu Han, Hugh J. Barnaby, Shimeng Yu, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae-Joon Kim:
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. IEEE Micro 39(6): 54-63 (2019) - [j18]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, Jae-sun Seo:
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3843-3853 (2019) - [c60]Zhewei Jiang, Shihui Yin, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-sun Seo:
Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration. ACSSC 2019: 1516-1521 - [c59]Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, Jae-Sun Seo:
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation. A-SSCC 2019: 145-148 - [c58]Deepak Kadetotad, Visar Berisha, Chaitali Chakrabarti, Jae-Sun Seo:
A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip. ESSCIRC 2019: 119-122 - [c57]Zhewei Jiang, Shihui Yin, Jae-Sun Seo, Mingoo Seok:
C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing. ESSCIRC 2019: 131-134 - [c56]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. FPL 2019: 166-172 - [c55]Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok:
XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism. ACM Great Lakes Symposium on VLSI 2019: 417-422 - [c54]Gaurav Srivastava, Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo:
Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks. ICASSP 2019: 1393-1397 - [c53]Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Shihui Yin, Jae-Sun Seo, Bipin Rajendran:
Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays. ICECS 2019: 438-441 - [c52]Sai Kiran Cherupally, Gaurav Srivastava, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, Jae-sun Seo:
ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. ISCAS 2019: 1-5 - [c51]Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo:
K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. ISLPED 2019: 1-6 - [c50]Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu:
Inference engine benchmarking across technological platforms from CMOS to RRAM. MEMSYS 2019: 471-479 - [c49]Paul N. Whatmough, Chuteng Zhou, Patrick Hansen, Shreyas K. Venkataramanaiah, Jae-sun Seo, Matthew Mattina:
FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning. MLSys 2019 - [c48]Mingoo Seok, Minhao Yang, Zhewei Jiang, Aurel A. Lazar, Jae-sun Seo:
Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks. VLSI-DAT 2019: 1-2 - [i8]Paul N. Whatmough, Chuteng Zhou, Patrick Hansen, Shreyas K. Venkataramanaiah, Jae-sun Seo, Matthew Mattina:
FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning. CoRR abs/1902.11128 (2019) - [i7]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR abs/1908.06724 (2019) - [i6]Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo:
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. CoRR abs/1909.07514 (2019) - 2018
- [j17]Arindam Basu, Meng-Fan Chang, Elisabetta Chicca, Tanay Karnik, Hai Helen Li, Jae-sun Seo:
Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 1-5 (2018) - [j16]Arindam Basu, Jyotibdha Acharya, Tanay Karnik, Huichu Liu, Hai Helen Li, Jae-sun Seo, Chang Song:
Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 6-27 (2018) - [j15]Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. 62: 14-23 (2018) - [j14]Yu Cao, Xin Li, Jae-sun Seo, Ganesh Dasika:
Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning. ACM J. Emerg. Technol. Comput. Syst. 14(2): 14:1-14:2 (2018) - [j13]Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim:
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition. ACM J. Emerg. Technol. Comput. Syst. 14(4): 42:1-42:19 (2018) - [j12]Robert D'Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao Huang, Nhut Tran, Armand Chery, Jae-sun Seo, Yu Cao, Dorothy C. Poppe, Sameer R. Sonkusale:
Process Scalability of Pulse-Based Circuits for Analog Image Convolution. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2929-2938 (2018) - [j11]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1354-1367 (2018) - [j10]Mohit Shah, Sairam Arunachalam, Jingcheng Wang, David T. Blaauw, Dennis Sylvester, Hun-Seok Kim, Jae-sun Seo, Chaitali Chakrabarti:
A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware. J. Signal Process. Syst. 90(5): 727-741 (2018) - [c47]Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu:
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC 2018: 574-579 - [c46]Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu:
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. DATE 2018: 1423-1428 - [c45]Avesta Sasan, Qi Zhu, Yanzhi Wang, Jae-sun Seo, Tinoosh Mohsenin:
Low Power and Trusted Machine Learning. ACM Great Lakes Symposium on VLSI 2018: 515 - [c44]Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Junseok Chae, Yu Cao, Visar Berisha:
Towards a Wearable Cough Detector Based on Neural Networks. ICASSP 2018: 2161-2165 - [c43]Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD 2018: 57 - [c42]Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, Chaitali Chakrabarti:
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks. SiPS 2018: 13-18 - [i5]Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo:
Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression. CoRR abs/1804.07370 (2018) - [i4]Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings:
Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain. CoRR abs/1805.08932 (2018) - 2017
- [j9]Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, Yu Cao:
Improving efficiency in sparse learning with the feedforward inhibitory motif. Neurocomputing 267: 141-151 (2017) - [j8]Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, Mingoo Seok:
Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities. IEEE J. Solid State Circuits 52(10): 2550-2562 (2017) - [c41]Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo:
Minimizing area and energy of deep learning hardware design using collective low precision and structured compression. ACSSC 2017: 1907-1911 - [c40]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo:
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC 2017: 21-22 - [c39]Shunti Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti, Jae-sun Seo:
Low-power neuromorphic speech recognition engine with coarse-grain sparsity. ASP-DAC 2017: 111-114 - [c38]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS 2017: 1-5 - [c37]Xiaoyang Mi, Hesam Fathi Moghadam, Jae-sun Seo:
Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators. DATE 2017: 1269-1272 - [c36]Shihui Yin, Chisung Bae, Sang Joon Kim, Jae-sun Seo:
Designing ECG-based physical unclonable function for security of wearable devices. EMBC 2017: 3509-3512 - [c35]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA 2017: 45-54 - [c34]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL 2017: 1-8 - [c33]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo:
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS 2017: 1-4 - [c32]Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
End-to-end scalable FPGA accelerator for deep residual networks. ISCAS 2017: 1-4 - [c31]Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim:
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. ISLPED 2017: 1-6 - [c30]Ricardo Tapiador-Morales, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim, Deepak Kadetotad, Jae-sun Seo:
Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs. IWANN (2) 2017: 271-282 - [i3]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR abs/1709.06206 (2017) - 2016
- [j7]Suyoung Bang, Jae-sun Seo, Leland Chang, David T. Blaauw, Dennis Sylvester:
A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering. IEEE J. Solid State Circuits 51(4): 919-929 (2016) - [j6]Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula:
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2873-2886 (2016) - [c29]Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, Mingoo Seok:
Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability. A-SSCC 2016: 289-292 - [c28]Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA 2016: 16-25 - [c27]Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL 2016: 1-8 - [c26]Ming Tu, Visar Berisha, Martin Woolf, Jae-sun Seo, Yu Cao:
Ranking the parameters of deep neural networks using the fisher information. ICASSP 2016: 2647-2651 - [c25]Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu:
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. ICCAD 2016: 15 - [c24]Deepak Kadetotad, Sairam Arunachalam, Chaitali Chakrabarti, Jae-sun Seo:
Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications. ICCAD 2016: 78 - [c23]Dawei Zhou, Jingrui He, Yu Cao, Jae-sun Seo:
Bi-Level Rare Temporal Pattern Detection. ICDM 2016: 719-728 - [c22]Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
High-performance face detection with CPU-FPGA acceleration. ISCAS 2016: 117-120 - [c21]