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ORCIDTakashi Takemoto
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2020 – today
- 2021
[j13]Kasho Yamamoto
, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura:
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits 56(1): 165-178 (2021)- [j12]Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki:
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. Soft Comput. 25(3): 1731-1749 (2021) - [c26]Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka:
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. A-SSCC 2021: 1-3 - [c25]Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka:
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. ISSCC 2021: 64-66 - 2020
- [j11]Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka:
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. IEEE J. Solid State Circuits 55(1): 145-156 (2020) - [c24]Chihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka:
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem. ASP-DAC 2020: 673-678 - [c23]Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura:
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC 2020: 138-140 - [i1]Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki:
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. CoRR abs/2004.03819 (2020)
2010 – 2019
- 2019
- [c22]Masanao Yamaoka, Takuya Okuyama, Masato Hayashi, Chihiro Yoshimura, Takashi Takemoto:
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems. CICC 2019: 1-8 - [c21]Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka:
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. ISSCC 2019: 52-54 - [c20]Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka:
A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems. VLSI Circuits 2019: 148- - 2018
- [j10]Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Hideo Arimoto, Masaru Kokubo, Tatemi Ido:
A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology. IEEE J. Solid State Circuits 53(5): 1518-1538 (2018) - [c19]Takashi Takemoto, Normann Mertig, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki, Masanao Yamaoka:
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. ReConFig 2018: 1-8 - [c18]Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki:
Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity. TPNC 2018: 111-123 - 2016
- [j9]Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Takahiro Nakamura, Yong Lee, Hideo Arimoto, Tatemi Ido:
A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver. IEICE Trans. Electron. 99-C(9): 1039-1047 (2016) - [c17]Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo:
A jitter-reduction packaging structure for a 56-Gb/s NRZ modulated optical receiver. OFC 2016: 1-3 - [c16]Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo, Tatemi Ido:
A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology. VLSI Circuits 2016: 1-2 - 2015
- [c15]Takashi Takemoto, Hiroki Yamashita, Yasunobu Matsuoka, Yong Lee, Masaru Kokubo:
An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects. CICC 2015: 1-4 - [c14]Koichiro Adachi, Yasunobu Matsuoka, Takashi Takemoto, Takanori Suzuki, Shigehisa Tanaka, Akira Nakanishi, Kazuhiko Naoe:
Wide-temperature-range 103.2 (25.8 × 4)-Gb/s optical link for data-center Interconnects using a 1.3-µm lens-integrated surface-emitting laser array. OFC 2015: 1-3 - [c13]Takashi Takemoto, Yasunobu Matsuoka, Yoshikazu Sugiyama, Hidenori Yonezawa, Hiroki Yamashita, Koichiro Adachi, Takahiro Nakamura, Etsuko Nomoto, Kouji Nakahara, Hideo Arimoto, Kenichi Osada, Tatemi Ido:
A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. OFC 2015: 1-3 - 2014
- [j8]Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura:
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. IEEE J. Solid State Circuits 49(2): 471-485 (2014) - [j7]Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka:
A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects. IEEE J. Solid State Circuits 49(10): 2259-2276 (2014) - [c12]Toru Yazaki, Norio Chujo, Hiroki Yamashita, Takashi Takemoto, Yong Lee, Yasunobu Matsuoka:
25-Gbps×4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS. ISCAS 2014: 2692-2695 - 2013
- [c11]Norio Chujo, Takashi Takemoto, Fumio Yuki, Hiroki Yamashita:
High-frequency circuit design for 25 Gb/s×4 optical transceiver. ASP-DAC 2013: 648-651 - [c10]Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka:
A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects. ISSCC 2013: 118-119 - [c9]Norio Chujo, Toru Yazaki, Toshiaki Takai, Daichi Kawamura, Yasunobu Matsuoka, Yong Lee, Toshiki Sugawara, Hiroki Yamashita, Takashi Takemoto, Yoshiaki Ishigami, Kinya Yamazaki, Yoshinori Sunaga, Naoki Matsushima:
A 25-Gb/s × 4-Ch, 8 × 8 mm2, 2.8-mm thick compact optical transceiver module for on-board optical interconnect. OFC/NFOEC 2013: 1-3 - [c8]Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Shinji Tsuji, Yong Lee, Koichiro Adachi, Kazunori Shinoda, Yasunobu Matsuoka, Toshiki Sugawara, Shinji Nishimura, Norio Chujo, Masaaki Nido, Kazuhiko Kurata, Junji Baba, Yoshinori Watanabe, Naoya Ikeda:
Compact and power-efficient 100-Gbps CMOS-based transceiver. OFC/NFOEC 2013: 1-3 - 2012
- [j6]Shinji Tsuji, Takashi Takemoto:
Optical Interconnects for Green Computers and Data Centers. Adv. Comput. 87: 125-201 (2012) - [c7]Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura:
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. VLSIC 2012: 106-107 - 2011
- [j5]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura:
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. IEEE J. Solid State Circuits 46(12): 3101-3112 (2011) - [c6]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura:
10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. ISSCC 2011: 148-150 - 2010
- [j4]Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito:
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. IEEE J. Solid State Circuits 45(12): 2838-2849 (2010) - [c5]Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura:
A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS. CICC 2010: 1-4 - [c4]Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Tatsuya Saito:
A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS. ISSCC 2010: 368-369
2000 – 2009
- 2009
- [j3]Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Masashi Kono, Tatsuya Saito:
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS. IEEE J. Solid State Circuits 44(12): 3539-3546 (2009) - [c3]Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito:
10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1st-order ΔΣ modulator. ISSCC 2009: 186-187 - 2008
- [c2]Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Masayoshi Yagyu, Ryo Nemoto, Takashi Takemoto, Tatsuya Saito, Norio Chujo, Keiichi Yamamoto, Hisaaki Kanai, Atsuhiro Hayashi:
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. ISSCC 2008: 98-99 - 2007
- [j2]Takashi Takemoto, Takashi Kohno, Kazuyuki Aihara:
Circuit Implementation and Dynamics of a Two-Dimensional MOSFET Neuron Model. Int. J. Bifurc. Chaos 17(2): 459-508 (2007) - 2006
- [j1]Takashi Takemoto, Takashi Kohno, Kazuyuki Aihara:
MOSFET implementation of class I* neurons coupled by gap junctions. Artif. Life Robotics 10(1): 1-5 (2006) - [c1]Yoshiyuki Kokojima, Kaoru Sugita, Takahiro Saito, Takashi Takemoto:
Resolution independent rendering of deformable vector objects using graphics hardware. SIGGRAPH Sketches 2006: 118
Coauthor Index
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