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2010 – 2019
- 2017
[j3]Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang:
A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration. ACM Trans. Design Autom. Electr. Syst. 22(2): 27:1-27:22 (2017)- 2016
- [j2]Yu-Ming Chang, Pi-Cheng Hsiu
, Yuan-Hao Chang, Chi-Hao Chen, Tei-Wei Kuo, Cheng-Yuan Michael Wang:
Improving PCM Endurance with a Constant-Cost Wear Leveling Design. ACM Trans. Design Autom. Electr. Syst. 22(1): 9:1-9:27 (2016) - 2015
- [j1]Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang:
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. ACM Trans. Archit. Code Optim. 12(2): 19:19:1-19:19:24 (2015) - [c5]Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang:
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. NVMSA 2015: 1-6 - 2014
- [c4]Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Shun-Chih Yu, Cheng-Yuan Michael Wang:
NVM duet: unified working memory and persistent store architecture. ASPLOS 2014: 455-470 - 2013
- [c3]Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang:
A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. ISSCC 2013: 222-223 - 2012
- [c2]Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang:
Age-based PCM wear leveling with nearly zero search cost. DAC 2012: 453-458 - [c1]Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang:
SECRET: Selective error correction for refresh energy reduction in DRAMs. ICCD 2012: 67-74
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