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2020 – today
- 2023
[j104]Akira Matsuzawa:
Sampling circuit issues in A/D converters and challenges for the solution. IEICE Electron. Express 20(13): 20232001 (2023)- [j103]Akira Matsuzawa:
A Brief History of Nyquist Analog-to-Digital Converters. IEICE Trans. Electron. 106(10): 493-505 (2023) - [c98]Akira Matsuzawa:
Shape the World with Mixed-Signal Integrated Circuits - Past, Present, and Future. ISSCC 2023: 13-22
2010 – 2019
- 2019
- [j102]Zule Xu, Anugerah Firdauzi
, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. IEICE Trans. Electron. 102-C(7): 520-529 (2019) - [j101]Yun Wang, Bangan Liu, Rui Wu, Hanli Liu, Aravind Tharayil Narayanan, Jian Pang, Ning Li, Toru Yoshioka, Yuki Terashima, Haosheng Zhang, Dexian Tang, Makihiko Katsuragi, Daeyoung Lee, Sung Tae Choi, Kenichi Okada, Akira Matsuzawa:
A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS. IEEE J. Solid State Circuits 54(5): 1363-1374 (2019) - [c97]Akira Matsuzawa:
A Universal ADC for Sensor Applications. 3DIC 2019: 1-4 - 2018
- [j100]Akira Matsuzawa, Masaya Miyahara:
SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier. IEICE Electron. Express 15(5) (2018) - [j99]Korkut Kaan Tokgoz, Seitaro Kawai, Kenichi Okada, Akira Matsuzawa:
Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS. IEICE Electron. Express 15(7): 20180067 (2018) - [j98]Bangan Liu, Yun Wang, Jian Pang, Haosheng Zhang, Dongsheng Yang, Aravind Tharayil Narayanan, Dae Young Lee, Sung Tae Choi, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. IEICE Trans. Electron. 101-C(2): 126-134 (2018) - [j97]Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa:
A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. IEICE Trans. Electron. 101-C(4): 187-196 (2018) - [j96]Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa:
A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells. IEICE Trans. Electron. 101-C(4): 197-205 (2018) - [j95]Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa:
A 7GS/s Complete-DDFS-Solution in 65nm CMOS. IEICE Trans. Electron. 101-C(4): 206-217 (2018) - [j94]Tohru Kaneko, Koji Hirose, Akira Matsuzawa:
A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits. IEICE Trans. Electron. 101-C(4): 224-232 (2018) - [j93]Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa:
A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS. IEEE J. Solid State Circuits 53(10): 2840-2849 (2018) - [c96]Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa:
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC 2018: 1-4 - [c95]Jian Sen Teh, Liter Siek, Abdel Martinez Alonso, Anugerah Firdauzi, Akira Matsuzawa:
A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. ISCAS 2018: 1-5 - [c94]Korkut Kaan Tokgoz, Shotaro Maki, Jian Pang, Noriaki Nagashima, Ibrahim Abdo, Seitaro Kawai, Takuya Fujimura, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa:
A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver. ISSCC 2018: 168-170 - [c93]Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa:
A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. ISSCC 2018: 246-248 - [c92]Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, Akira Matsuzawa:
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. ISSCC 2018: 444-446 - [c91]Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira Matsuzawa:
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. VLSI Circuits 2018: 115-116 - 2017
- [j92]Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. IEICE Trans. Electron. 100-C(3): 259-267 (2017) - [j91]Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa:
A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input. IEICE Trans. Electron. 100-C(6): 539-547 (2017) - [j90]Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa:
High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. IEICE Trans. Electron. 100-C(6): 548-559 (2017) - [j89]Yun Wang, Makihiko Katsuragi, Kenichi Okada, Akira Matsuzawa:
A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS. IEICE Trans. Electron. 100-C(6): 568-575 (2017) - [j88]Mitsutoshi Sugawara, Zule Xu, Akira Matsuzawa:
Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs. IEICE Trans. Electron. 100-C(6): 576-583 (2017) - [j87]Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits 52(11): 2871-2891 (2017) - [c90]Akira Matsuzawa, Masaya Miyahara:
SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier. ASICON 2017: 24-27 - [c89]Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON 2017: 1025-1028 - [c88]Korkut Kaan Tokgoz, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa:
W-band ultra-high data-rate 65nm CMOS wireless transceiver. ASP-DAC 2017: 5-6 - [c87]Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC 2017: 13-14 - [c86]Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa:
A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS. A-SSCC 2017: 181-184 - [c85]Masaya Miyahara, Akira Matsuzawa:
An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. CICC 2017: 1-4 - [c84]Tuan Minh Vo, Akira Matsuzawa:
An automatic dynamic range adaptation algorithm for capacitive sensor interface circuits. ECCTD 2017: 1-4 - [c83]Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa:
A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS. ESSCIRC 2017: 151-154 - [c82]Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa:
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. ISSCC 2017: 150-151 - [c81]Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. ISSCC 2017: 424-425 - 2016
- [j86]Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC. IEICE Trans. Electron. 99-C(6): 623-631 (2016) - [j85]Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. IEICE Trans. Electron. 99-C(6): 632-640 (2016) - [j84]Lilan Yu, Masaya Miyahara, Akira Matsuzawa:
Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques. IEICE Trans. Electron. 99-C(6): 641-650 (2016) - [j83]Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC. IEICE Trans. Electron. 99-C(8): 963-973 (2016) - [j82]Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa:
A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture. IEICE Trans. Electron. 99-C(10): 1200-1210 (2016) - [j81]Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2435-2443 (2016) - [j80]Yu Hou, Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2473-2482 (2016) - [j79]Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. IEEE J. Solid State Circuits 51(5): 1246-1260 (2016) - [j78]Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits 51(6): 1385-1397 (2016) - [j77]Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. IEEE J. Solid State Circuits 51(7): 1630-1640 (2016) - [j76]Lilan Yu, Masaya Miyahara, Akira Matsuzawa:
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers. IEEE J. Solid State Circuits 51(10): 2210-2221 (2016) - [j75]Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. IEEE J. Solid State Circuits 51(10): 2345-2356 (2016) - [c80]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC 2016: 1-2 - [c79]Aravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa:
A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. ASP-DAC 2016: 5-6 - [c78]Lilan Yu, Masaya Miyahara, Akira Matsuzawa:
A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers. A-SSCC 2016: 65-68 - [c77]Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. A-SSCC 2016: 109-112 - [c76]Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain. A-SSCC 2016: 309-312 - [c75]Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC 2016: 197-200 - [c74]Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A 2 GHz 3.1 mW type-I digital ring-based PLL. ESSCIRC 2016: 205-208 - [c73]Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder. ESSCIRC 2016: 249-252 - [c72]Tohru Kaneko, Yuya Kimura, Koji Hirose, Masaya Miyahara, Akira Matsuzawa:
A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter. ESSCIRC 2016: 253-256 - [c71]Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa:
A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. ISCAS 2016: 57-60 - [c70]Korkut Kaan Tokgoz, Shotaro Maki, Seitaro Kawai, Noriaki Nagashima, Jun Emmei, Masato Dome, Hisashi Kato, Jian Pang, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Yuuki Seo, Kimsrun Lim, Shinji Sato, Ning Li, Kengo Nakata, Kenichi Okada, Akira Matsuzawa:
13.3 A 56Gb/s W-band CMOS wireless transceiver. ISSCC 2016: 242-243 - [c69]Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC 2016: 248-249 - 2015
- [j74]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa:
A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. IEICE Electron. Express 12(15): 20150531 (2015) - [j73]Korkut Kaan Tokgoz, Kimsrun Lim, Seitarou Kawai, Nurul Fajri, Kenichi Okada, Akira Matsuzawa:
Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Electron. 98-C(1): 35-44 (2015) - [j72]Yu Hou, Takamoto Watanabe, Masaya Miyahara, Akira Matsuzawa:
An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(2): 466-475 (2015) - [j71]Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa:
Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(2): 476-484 (2015) - [j70]Rui Wu, Wei Deng, Shinji Sato, Takuichi Hirano, Ning Li, Takeshi Inoue, Hitoshi Sakane, Kenichi Okada, Akira Matsuzawa:
A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections. IEICE Trans. Electron. 98-C(4): 304-314 (2015) - [j69]Tohru Kaneko, Masaya Miyahara, Akira Matsuzawa:
A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency. IEICE Trans. Electron. 98-C(4): 315-321 (2015) - [j68]Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. IEICE Trans. Electron. 98-C(6): 471-479 (2015) - [j67]Kento Kimura, Aravind Tharayil Narayanan, Kenichi Okada, Akira Matsuzawa:
An AM-PM Noise Mitigation Technique in Class-C VCO. IEICE Trans. Electron. 98-C(12): 1161-1170 (2015) - [j66]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits 50(1): 68-80 (2015) - [j65]James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa:
An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers. IEEE J. Solid State Circuits 50(6): 1399-1411 (2015) - [j64]James Lin, Ibuki Mano, Masaya Miyahara, Akira Matsuzawa:
Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1518-1527 (2015) - [c68]Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa:
A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture. ASICON 2015: 1-4 - [c67]Akira Matsuzawa:
Automated design strategy for high performance mixed signal circuits. ASICON 2015: 1-4 - [c66]Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC 2015: 2-3 - [c65]Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A tail-current modulated VCO with adaptive-bias scheme. ASP-DAC 2015: 36-37 - [c64]Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC 2015: 42-43 - [c63]Zule Xu, Masaya Miyahara, Akira Matsuzawa:
A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. A-SSCC 2015: 1-4 - [c62]Lilan Yu, Masaya Miyahara, Akira Matsuzawa:
A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers. A-SSCC 2015: 1-4 - [c61]Teerachot Siriburanon, Hanli Liu, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa:
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. ESSCIRC 2015: 76-79 - [c60]Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. ESSCIRC 2015: 380-383 - [c59]Ning Li, Takeshi Inoue, Takuichi Hirano, Jian Pang, Rui Wu, Kenichi Okada, Hitoshi Sakane, Akira Matsuzawa:
Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process. ESSDERC 2015: 254-257 - [c58]Akira Matsuzawa:
High data rate 60 GHz CMOS transceiver design. ISPACS 2015: 1-6 - [c57]Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. ISSCC 2015: 1-3 - [c56]Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC 2015: 1-3 - [c55]Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
19.5 An HCI-healing 60GHz CMOS transceiver. ISSCC 2015: 1-3 - [c54]Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC. VLSIC 2015: 64- - 2014
- [j63]Sanroku Tsukamoto, Masaya Miyahara, Akira Matsuzawa:
A 7-bit 1-GS/s Flash ADC with Background Calibration. IEICE Trans. Electron. 97-C(4): 298-307 (2014) - [j62]Jeonghoon Han, Masaya Miyahara, Akira Matsuzawa:
Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator. IEICE Trans. Electron. 97-C(4): 316-324 (2014) - [j61]Rui Wu, Yuuki Tsukui, Ryo Minami, Kenichi Okada, Akira Matsuzawa:
A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation. IEICE Trans. Electron. 97-C(8): 803-812 (2014) - [j60]James Lin, Masaya Miyahara, Akira Matsuzawa:
An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2400-2410 (2014) - [j59]Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits 49(1): 50-60 (2014) - [j58]Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. IEEE J. Solid State Circuits 49(9): 1984-1994 (2014) - [c53]Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC 2014: 21-22 - [c52]Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. ASP-DAC 2014: 25-26 - [c51]James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa:
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. A-SSCC 2014: 85-88 - [c50]Rui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs. A-SSCC 2014: 181-184 - [c49]Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI. A-SSCC 2014: 285-288 - [c48]Aravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. ESSCIRC 2014: 343-346 - [c47]Takamoto Watanabe, Yu Hou, Masaya Miyahara, Akira Matsuzawa:
All-digital 0.016mm2 reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS. ICECS 2014: 21-24 - [c46]Tomohito Terasawa, Yuji Kamiya, Hiroyuki Kawashima, Kenichiro Imai, Masanobu Suzuki, Takamoto Watanabe, Nobuyuki Taguchi, Manabu Sawada, Yu Hou, Yoshiyuki Hirooka, Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa:
Radio receiver front-end using time-based all-digital ADC (TAD). ICECS 2014: 471-473 - [c45]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. ISSCC 2014: 266-267 - [c44]Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa:
20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. ISSCC 2014: 346-347 - [c43]