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"32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS."

Yoshiyasu Doi et al. (2013)

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DOI: 10.1109/ISSCC.2013.6487626

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  - conf/isscc/DoiSDCHMHKYTT13
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  - https://dblp.org/rec/conf/isscc/DoiSDCHMHKYTT13
Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. ISSCC 2013: 36-37

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