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2010 – 2019
- 2018
[c9]Michael Clinton, Rajinder Singh, Marty Tsai, Shayan Zhang, Bryan Sheffield, Jonathan Chang:
A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications. ISSCC 2018: 200-201- 2017
- [c8]Michael Clinton, Hank Cheng, Hung-Jen Liao, Robin Lee, Ching-Wei Wu, Johnny Yang, Hau-Tai Hsieh, Frank Wu, Jung-Ping Yang, Atul Katoch, Arun Achyuthan, Donald Mikan, Bryan Sheffield, Jonathan Chang:
12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications. ISSCC 2017: 210-211 - 2014
- [j2]Sudhanshu Khanna, Steven Bartling, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams:
An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at VDD = 0 V Achieving Zero Leakage With < 400-ns Wakeup Time for ULP Applications. IEEE J. Solid State Circuits 49(1): 95-106 (2014) - 2013
- [c7]Michael Clinton, Atsushi Kawasumi:
Session 18 overview: Advanced embedded SRAM. ISSCC 2013: 314-315 - [c6]Steven Bartling, Sudhanshu Khanna, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams:
An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions. ISSCC 2013: 432-433 - 2012
- [j1]Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan:
A Low-Voltage 1 Mb FRAM in 0.13 µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin. IEEE J. Solid State Circuits 47(1): 141-150 (2012) - [c5]Leland Chang, Michael Clinton:
Session 13 overview: High-performance embedded SRAM: Memory subcommittee. ISSCC 2012: 228-229 - 2011
- [c4]Michael Clinton, Clive Bittlestone, G. Girishankar, Viet Le, Vinod Menezes:
Design and technology interaction beyond 32nm. CICC 2011: 1-9 - [c3]Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan:
A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS. ISSCC 2011: 208-210
2000 – 2009
- 2008
- [c2]Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko:
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. ISSCC 2008: 258-259 - 2007
- [c1]Philippe Royannez, Hugh Mair, Michael Clinton, Uming Ko:
Solutions for logic and processor core design at the 45nm technology node & and below. ICECS 2007: 923-926
Coauthor Index
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