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2020 – today
- 2024
[j55]Zonghao Li, Anthony Chan Carusone:
An Open-Source AMS Circuit Optimization Framework Based on Reinforcement Learning - From Specifications to Layouts. IEEE Access 12: 150032-150045 (2024)- [c64]Bangda Bender Yang, Anthony Chan Carusone:
Design of a Linearized Power-Efficient Dynamic Amplifier in 22nm FDSOI. ISCAS 2024: 1-5 - [c63]Richard Barrie, Ming Yang, Hossein Shakiba, Anthony Chan Carusone:
An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems. MWSCAS 2024: 282-285 - [c62]Durand Jarrett-Amor, Tony Chan Carusone:
A 16 Gbps, 0.126 pJ/bit, Single-Ended TIA Driver with Impedance Peaking Control for SBD D2D Links. NewCAS 2024: 45-49 - 2023
- [j54]Dhruv Patel
, Alireza Sharif Bakhtiar, Tony Chan Carusone:
A 112-Gb/s - 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes. IEEE J. Solid State Circuits 58(3): 771-784 (2023) - [c61]Zonghao Li, Anthony Chan Carusone:
Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process. ICCAD 2023: 1-9 - [c60]Mohammed Wagih Ismail, Xilin Liu, Tony Chan Carusone:
Inductorless Bandpass Noise-Shaping Continuous-Time Pipelined ADC Architectures. ISCAS 2023: 1-5 - [c59]Durand Jarrett-Amor, Kunal Yadav, Danny Zhang, Bangda Yang, Sadegh Jalali, Tony Chan Carusone:
A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links. ISCAS 2023: 1-5 - 2022
- [j53]Hong Zhang, Ahmad Hassan, Paul Chen, W. Martin Snelgrove, Anthony Chan Carusone:
Estimation of Broadband Time-Interleaved ADC's Impairments and Performance Using Only Single-Tone Measurements. IEEE Access 10: 50403-50417 (2022) - [j52]Behraz Vatankhahghadim, Bahaa Radi, Masum Hossain, Anthony Chan Carusone:
Spectrally Efficient DMT Operation With BER-Informed Dynamic Bit and Power Loading. IEEE Access 10: 122061-122073 (2022) - [j51]Qingnan Yu, Tony Chan Carusone, Antonio Liscidini:
Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law. IEEE Open J. Circuits Syst. 3: 38-49 (2022) - [j50]Kunal Yadav, Ping-Hsuan Hsieh, Anthony Chan Carusone:
Loop Dynamics Analysis of PAM-4 Mueller-Muller Clock and Data Recovery System. IEEE Open J. Circuits Syst. 3: 216-227 (2022) - [j49]Mohammed Wagih Ismail, Hajime Shibata, Zhao Li, Sharvil Patil, Tony Chan Carusone:
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4731-4740 (2022) - [j48]Foad Arvani, Tony Chan Carusone:
A Reconfigurable 5-Channel Ring-Oscillator-Based TDC for Direct Time-of-Flight 3D Imaging. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2408-2412 (2022) - [j47]Bahaa Radi, Diaaeldin Abdelrahman, Odile Liboiron-Ladouceur, Glenn E. R. Cowan, Tony Chan Carusone:
Optimal Optical Receivers in Nanoscale CMOS: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2604-2609 (2022) - [c58]Dhruv Patel, Alireza Sharif Bakhtiar, Anthony Chan Carusone:
A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes. CICC 2022: 1-2 - [c57]Yi Fan Zhang, Joshua Liang, Tony Chan Carusone:
Design Considerations for Time-Modulated Injection-Locked Phase Interpolators and Rotators. ISCAS 2022: 1719-1723 - 2021
- [j46]Behraz Vatankhahghadim, Nijwm Wary, James Bailey, Anthony Chan Carusone:
A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s. IEEE Open J. Circuits Syst. 2: 78-90 (2021) - [j45]Foad Arvani, Anthony Chan Carusone:
Peak-SNR Analysis of CMOS TDCs for SPAD-Based TCSPC 3D Imaging Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 893-897 (2021) - [c56]Ming Yang, Shayan Shahramian, Henry Wong, Peter Krotnev, Anthony Chan Carusone:
Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers. ISCAS 2021: 1-5 - [c55]Tony Chan Carusone, Sudip Shekhar, Yohan Frans, Wei-Zen Chen, Thomas Toifl, Munehiko Nagatani, Franz Dielacher, William Redman-White:
F6: Optical and Electrical Transceivers for 400GbE and Beyond. ISSCC 2021: 533-536 - 2020
- [j44]Tony Chan Carusone, Mingoo Seok, Hsie-Chia Chang, Meng-Fan Chang:
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 55(1): 3-5 (2020) - [j43]Ming Yang, Shayan Shahramian, Hossein Shakiba, Henry Wong, Peter Krotnev, Anthony Chan Carusone:
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 284-297 (2020) - [c54]Paul Wenbo Chen, Nijwm Wary, Luke Wang, Qiwei Wang, Anthony Chan Carusone:
All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs. ISCAS 2020: 1-5 - [c53]Behraz Vatankhahghadim, Nijwm Wary, Anthony Chan Carusone:
Discrete Multitone Signalling for Wireline Communication. ISCAS 2020: 1-5 - [c52]Rudraneil Saha, Anthony Chan Carusone:
An Adaptive Spatial Blocker Cancellation Receiver for Multiple Antenna Systems. NEWCAS 2020: 86-89
2010 – 2019
- 2019
- [j42]Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone:
A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET. IEEE J. Solid State Circuits 54(2): 452-462 (2019) - [c51]Foad Arvani, Tony Chan Carusone, Edward S. Rogers:
TDC Sharing in SPAD-Based Direct Time-of-Flight 3D Imaging Applications. ISCAS 2019: 1-5 - [c50]Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto:
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. ISSCC 2019: 482-484 - 2018
- [j41]Qiwei Wang, Hajime Shibata, Antonio Liscidini, Anthony Chan Carusone:
A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers. IEEE J. Solid State Circuits 53(3): 681-691 (2018) - [j40]Hong Zhang, Xipeng Liu, Jie Zhang, Hongshuai Zhang, Jijun Li, Ruizhi Zhang, Shuai Chen, Anthony Chan Carusone:
A Nano-Watt MOS-Only Voltage Reference With High-Slope PTAT Voltage Generators. IEEE Trans. Circuits Syst. II Express Briefs 65-II(1): 1-5 (2018) - [j39]Kevin Banovic, Anthony Chan Carusone:
A Sub-mW Integrating Mixer SAR Spectrum Sensor for Portable Cognitive Radio Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 1110-1119 (2018) - [j38]Hong Zhang, Junqiang Sun, Jie Zhang, Ruizhi Zhang, Anthony Chan Carusone:
A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1763-1776 (2018) - [c49]Foad Arvani, Tony Chan Carusone:
Direct Time-of-Flight TCSPC Analytical Modeling Including Dead-Time Effects. ISCAS 2018: 1-4 - [c48]Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone:
A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET. ISSCC 2018: 110-112 - 2017
- [j37]Luke Wang, Marc-Andre LaCroix, Anthony Chan Carusone:
A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1367-1371 (2017) - [j36]Shuai Chen, Luke Wang, Hong Zhang, Rosanah Murugesu, Dustin Dunwell, Anthony Chan Carusone:
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2552-2560 (2017) - [c47]Alireza Sharif Bakhtiar, Michael G. Lee, Anthony Chan Carusone:
A 40-Gbps 0.5-pJ/bit VCSEL driver in 28nm CMOS with complex zero equalizer. CICC 2017: 1-4 - [c46]Alireza Sharif Bakhtiar, Michael G. Lee, Anthony Chan Carusone:
Low-power CMOS receivers for short reach optical communication. CICC 2017: 1-8 - [c45]Qiwei Wang, Hajime Shibata, Anthony Chan Carusone, Antonio Liscidini:
A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS. CICC 2017: 1-4 - [c44]Kevin Banovic, Tony Chan Carusone:
A sub-mW spectrum sensing architecture for portable IEEE 802.22 cognitive radio applications. ISCAS 2017: 1-4 - [c43]Qiwei Wang, Antonio Liscidini, Anthony Chan Carusone:
Filtering ADCs for wireless receivers: A survey. MWSCAS 2017: 997-1000 - 2016
- [j35]Victor Kozlov, Anthony Chan Carusone:
Capacitively-Coupled CMOS VCSEL Driver Circuits. IEEE J. Solid State Circuits 51(9): 2077-2090 (2016) - [j34]Alireza Sharif Bakhtiar, Anthony Chan Carusone:
A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE. IEEE J. Solid State Circuits 51(11): 2679-2689 (2016) - [j33]Behzad Dehlaghi, Anthony Chan Carusone:
A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication. IEEE J. Solid State Circuits 51(11): 2690-2701 (2016) - [j32]Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone:
Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs. IEEE J. Solid State Circuits 51(12): 3192-3203 (2016) - [c42]Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone:
23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs. ISSCC 2016: 410-411 - 2015
- [j31]Shayan Shahramian, Anthony Chan Carusone:
A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS. IEEE J. Solid State Circuits 50(7): 1722-1735 (2015) - [j30]Shayan Shahramian, Anthony Chan Carusone:
Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS". IEEE J. Solid State Circuits 50(10): 2463 (2015) - [c41]Behzad Dehlaghi, Anthony Chan Carusone:
A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS. CICC 2015: 1-4 - [c40]Amer Samarah, Anthony Chan Carusone:
Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition. ISCAS 2015: 545-548 - [c39]Amer Samarah, Anthony Chan Carusone:
Cycle-slipping pull-in range of bang-bang PLLs. NEWCAS 2015: 1-4 - [c38]M. Shibata, Anthony Chan Carusone:
A 26-Gb/s 1.80-pJ/b CMOS-driven transmitter for 850-nm common-cathode VCSELs. OFC 2015: 1-3 - [c37]Alireza Sharif Bakhtiar, Anthony Chan Carusone:
A 19.6-Gbps CMOS optical receiver with local feedback IIR DFE. VLSIC 2015: 116- - 2014
- [c36]Luke Wang, Qiwei Wang, Anthony Chan Carusone:
Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS. ESSCIRC 2014: 207-210 - [c35]Shayan Shahramian, Anthony Chan Carusone:
A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS. ESSCIRC 2014: 439-442 - [c34]Mike Bichan, Dustin Dunwell, Qiwei Wang, Anthony Chan Carusone:
A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC. ISCAS 2014: 1320-1323 - 2013
- [j29]Amer Samarah, Anthony Chan Carusone:
A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC. IEEE J. Solid State Circuits 48(8): 1829-1841 (2013) - [j28]Dustin Dunwell, Anthony Chan Carusone:
Modeling Oscillator Injection Locking Using the Phase Domain Response. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2823-2833 (2013) - [c33]Dustin Dunwell, Atul Gupta, Anthony Chan Carusone:
Channel characterization using jitter measurements. ISCAS 2013: 2666-2669 - [c32]Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner:
F5: Frequency generation and clock distribution. ISSCC 2013: 508-509 - 2012
- [j27]Kentaro Yamamoto, Anthony Chan Carusone:
A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs. IEEE J. Solid State Circuits 47(8): 1866-1883 (2012) - [j26]Shayan Shahramian, Hemesh Yasotharan, Anthony Chan Carusone:
Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters. IEEE Trans. Circuits Syst. II Express Briefs 59-II(6): 326-330 (2012) - [c31]Dustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble:
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on. CICC 2012: 1-4 - [c30]Amer Samarah, Anthony Chan Carusone:
A digital phase-locked loop with calibrated coarse and stochastic fine TDC. CICC 2012: 1-4 - [c29]Amer Samarah, Anthony Chan Carusone:
A dead-zone free and linearized digital PLL. ICECS 2012: 801-804 - [c28]Ken Chang, Tony Chan Carusone, Ali Sheikholeslami, Bob Payne, Miki Moyal, John T. Stonick, Hisakatsu Yamaguchi:
10-40 Gb/s I/O design for data communications. ISSCC 2012: 502-503 - 2011
- [j25]Shahriar Shahramian, Adam Hart, Alexander Tomkins, Anthony Chan Carusone, Patrice Garcia, Pascal Chevalier, Sorin P. Voinigescu:
Design of a Dual W- and D-Band PLL. IEEE J. Solid State Circuits 46(5): 1011-1022 (2011) - [j24]Masum Hossain, Anthony Chan Carusone:
7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS. IEEE J. Solid State Circuits 46(6): 1337-1348 (2011) - [j23]Anthony Chan Carusone, Hemesh Yasotharan, Tony Shuo-Chun Kao:
CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors. IEEE J. Solid State Circuits 46(8): 1832-1842 (2011) - [c27]Kentaro Yamamoto, Anthony Chan Carusone:
A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs. CICC 2011: 1-4 - 2010
- [j22]Masum Hossain, Anthony Chan Carusone:
5-10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS. IEEE J. Solid State Circuits 45(3): 524-537 (2010) - [j21]Masum Hossain, Anthony Chan Carusone:
Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial-Response Channels. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 270-279 (2010) - [j20]Tony Shuo-Chun Kao, Faisal A. Musa, Anthony Chan Carusone:
A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(11): 2844-2857 (2010) - [c26]Anthony Chan Carusone, Hemesh Yasotharan, Tony Shuo-Chun Kao:
Progress and trends in multi-Gbps optical receivers with CMOS integrated photodetectors. CICC 2010: 1-8 - [c25]Dustin Dunwell, Anthony Chan Carusone:
Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver. CICC 2010: 1-4 - [c24]Dustin Dunwell, Anthony Chan Carusone:
A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS. ISCAS 2010: 205-208 - [c23]Masum Hossain, Anthony Chan Carusone:
A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS. ISSCC 2010: 158-159
2000 – 2009
- 2009
- [j19]Shahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone:
A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees. IEEE J. Solid State Circuits 44(6): 1709-1720 (2009) - [j18]Lawrence T. Clark, Anthony Chan Carusone, Payam Heydari:
Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 44(8): 2083-2084 (2009) - [j17]Masum Hossain, Anthony Chan Carusone:
CMOS Oscillators for Clock Distribution and Injection-Locked Deskew. IEEE J. Solid State Circuits 44(8): 2138-2153 (2009) - [j16]Anthony Chan Carusone, Yehea Ismail, Un-Ku Moon, Hanspeter Schmid, Wouter A. Serdijn, Gianluca Setti:
Guest Editorial Special Issue on ISCAS 2008. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 861-864 (2009) - [j15]Anthony Chan Carusone, Un-Ku Moon:
Introducing Jump-Start Tutorials. IEEE Trans. Circuits Syst. II Express Briefs 56-II(8): 613 (2009) - [j14]Anthony Chan Carusone, Horace Cheng, Faisal A. Musa:
A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1794-1806 (2009) - [c22]Anthony Chan Carusone, Franco Maloberti:
An Anti-aliasing Multi-rate SigmaDelta Modulator. ISCAS 2009: 1329-1332 - 2008
- [j13]Kentaro Yamamoto, Anthony Chan Carusone, Francis P. Dawson:
A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR. IEEE J. Solid State Circuits 43(8): 1772-1782 (2008) - [j12]Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
Power Reduction Techniques for LDPC Decoders. IEEE J. Solid State Circuits 43(8): 1835-1845 (2008) - [j11]Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 74-78 (2008) - [j10]Jennifer Pham, Anthony Chan Carusone:
A Time-Interleaved DeltaSigma-DAC Architecture Clocked at the Nyquist Rate. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 858-862 (2008) - [c21]Masum Hossain, Anthony Chan Carusone:
20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS. CICC 2008: 447-450 - [c20]Mike Bichan, Anthony Chan Carusone:
A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing. CICC 2008: 611-614 - [c19]Horace Cheng, Anthony Chan Carusone:
A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOS. CICC 2008: 635-638 - [c18]Anthony Chan Carusone:
High-performance chip-to-chip signaling. ICECS 2008: 16 - [c17]Faisal A. Musa, Anthony Chan Carusone:
A passive filter aided timing recovery scheme. ISCAS 2008: 3065-3068 - 2007
- [j9]Tuna B. Tarim, Anthony Chan Carusone:
Editorial ISCAS 2006 Special Section on Analog Circuits and Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(1): 191-192 (2007) - [j8]Faisal A. Musa, Anthony Chan Carusone:
Modeling and Design of Multilevel Bang-Bang CDRs in the Presence of ISI and Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(10): 2137-2147 (2007) - [c16]Kentaro Yamamoto, Anthony Chan Carusone, Francis P. Dawson:
A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR. CICC 2007: 65-68 - [c15]Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. CICC 2007: 459-462 - [c14]Mike Bichan, Anthony Chan Carusone:
Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links. ISCAS 2007: 189-192 - 2006
- [j7]Jonathan Sewter, Anthony Chan Carusone:
A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s. IEEE J. Solid State Circuits 41(4): 909-917 (2006) - [j6]Jonathan Sewter, Anthony Chan Carusone:
A 3-Tap FIR Filter With Cascaded Distributed Tap Amplifiers for Equalization Up to 40 Gb/s in 0.18-$mu$m CMOS. IEEE J. Solid State Circuits 41(8): 1919-1929 (2006) - [j5]Adesh Garg, Anthony Chan Carusone, Sorin P. Voinigescu:
A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology. IEEE J. Solid State Circuits 41(10): 2224-2232 (2006) - [j4]Shahriar Shahramian, Anthony Chan Carusone, Sorin P. Voinigescu:
Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology. IEEE J. Solid State Circuits 41(10): 2233-2240 (2006) - [j3]Anthony Chan Carusone:
An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 807-811 (2006) - [j2]Faisal A. Musa, Anthony Chan Carusone:
A Baud-Rate Timing Recovery Scheme With a Dual-Function Analog Filter. IEEE Trans. Circuits Syst. II Express Briefs 53-II(12): 1393-1397 (2006) - [c13]Shahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone:
A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology. CICC 2006: 493-496 - [c12]Masum Hossain, Anthony Chan Carusone:
A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-μm CMOS. CICC 2006: 829-832 - [c11]Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
A bit-serial approximate min-sum LDPC decoder and FPGA implementation. ISCAS 2006 - 2005
- [c10]Jonathan Sewter, Anthony Chan Carusone:
A 40 Gb/s transversal filter in 0.18 μm CMOS using distributed amplifiers. CICC 2005: 417-420 - [c9]Anthony Chan Carusone:
Jitter equalization for binary baseband communication. ISCAS (2) 2005: 936-939 - [c8]Jonathan Sewter, Anthony Chan Carusone:
A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems. ISCAS (2) 2005: 1521-1524 - [c7]Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity. ISCAS (5) 2005: 5194-5197 - 2004
- [c6]Shahriar Shahramian, Tony Chan Carusone:
Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization. ISCAS (3) 2004: 489-492 - 2003
- [j1]Anthony Chan Carusone, David A. Johns:
Digital LMS adaptation of analog filters without gradient information. IEEE Trans. Circuits Syst. II Express Briefs 50(9): 539-552 (2003) - [c5]Faisal A. Musa, Anthony Chan Carusone:
Clock recovery in high-speed multilevel serial links. ISCAS (5) 2003: 449-452 - [c4]Denis Daly, Anthony Chan Carusone:
A sigma-delta based open-loop frequency modulator. ISCAS (1) 2003: 929-932 - 2002
- [c3]Anthony Chan Carusone, David A. Johns:
Analog filter adaptation using a dithered linear search algorithm. ISCAS (4) 2002: 269-272 - [c2]Anthony Chan Carusone, David A. Johns:
A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes. ISCAS (4) 2002: 635-638
1990 – 1999
- 1999
- [c1]Anthony Chan Carusone, David A. Johns:
Obtaining digital gradient signals for analog adaptive filters. ISCAS (3) 1999: 54-57
Coauthor Index
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last updated on 2024-10-30 21:32 CET by the dblp team
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