Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDYuan Wang 0001
Person information
- affiliation: Peking University, Institute of Microelectronics, Beijing, China
Other persons with the same name
- Yuan Wang — disambiguation page
- Yuan Wang 0002
![[0000-0002-5193-8379]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-5193-8379")
— Tianjin University, State Key Laboratory of Precision Measurement Technology and Instrument, China - Yuan Wang 0003 — National University of Singapore, Department of Industrial and Systems Engineering, Singapore
- Yuan Wang 0004 — Nanjing University, National Key Laboratory for Novel Software Technology, China
- Yuan Wang 0005 — Florida Atlantic University, Department of Mathematical Sciences, Boca Raton, FL, USA (and 1 more)
- Yuan Wang 0006 — Peking University, Institute of Remote Sensing and GIS, Beijing, China
- Yuan Wang 0007 — Georgia Institute of Technology, Atlanta, GA, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
[j35]Jiahao Song, Xiyuan Tang, Xin Qiao, Yuan Wang, Runsheng Wang, Ru Huang:
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1835-1845 (2023)- [j34]Kefei Liu, Xiaoxin Cui, Xiang Ji, Yisong Kuang, Chenglong Zou, Yi Zhong, Kanglin Xiao, Yuan Wang:
Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1590-1594 (2023) - [c47]Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang:
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization. CICC 2023: 1-2 - [c46]Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Yuan Wang, Runsheng Wang, Ru Huang:
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. CICC 2023: 1-2 - [c45]Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang:
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. ISSCC 2023: 176-177 - [i4]Xiaochen Hao, Zijian Ding, Jieming Yin, Yuan Wang, Yun Liang:
ALEGO: Towards Cost-Aware Architecture and Integration Co-Design for Chiplet-based Spatial Accelerators. CoRR abs/2302.11256 (2023) - 2022
- [j33]Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang:
A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. Microelectron. J. 126: 105506 (2022) - [j32]Chenglong Zou, Xiaoxin Cui, Guang Chen, Shuo Feng, Kefei Liu, Xinan Wang, Yuan Wang:
Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor. Microelectron. J. 129: 105612 (2022) - [j31]Zilong Shen, Yize Wang, Yunhao Li, Xing Zhang, Yuan Wang:
A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1547-1551 (2022) - [j30]Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang:
A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2977-2981 (2022) - [j29]Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang:
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1631-1641 (2022) - [c44]Weichen Xu, Jian Cao, Tianhao Fu, Hongyi Yao, Yuan Wang:
Boosting Dense Long-Tailed Object Detection from Data-Centric View. ACCV (3) 2022: 558-574 - [c43]Kefei Liu, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Yi Zhong, Kanglin Xiao, Yuan Wang:
A Full-Neuron Memory Model Designed for Neuromorphic Systems. AICAS 2022: 138-141 - [c42]Xiuping Cui, Xiaochen Hao, Yun Liang, Guangyu Sun, Xiaoxin Cui, Yuan Wang, Ru Huang:
A Mapping Model of SNNs to Neuromorphic Hardware. AICAS 2022: 206-209 - [c41]Chenglong Zou, Xiaoxin Cui, Yisong Kuang, Yuan Wang, Xinan Wang:
A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition. AICAS 2022: 332-335 - [c40]Wenyu Sun, Jian Cao, Pengtao Xu, Xiangcheng Liu, Yuan Zhang, Yuan Wang:
An Once-for-All Budgeted Pruning Framework for ConvNets Considering Input Resolution. CVPR Workshops 2022: 2608-2617 - [c39]Qingyu Guo, Xiaoxin Cui, Jian Zhang, Aifei Zhang, Xinjie Guo, Yuan Wang:
A 4-bit Integer-Only Neural Network Quantization Method Based on Shift Batch Normalization. ISCAS 2022: 707-711 - [c38]Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Nanbing Pan, Xin'an Wang, Yuan Wang:
A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. ISCAS 2022: 2551-2555 - [c37]Nanbing Pan, Xiaoxin Cui, Xin Qiao, Kanglin Xiao, Qingyu Guo, Yuan Wang:
A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro. ISCAS 2022: 2561-2565 - [c36]Yisong Kuang, Xiaoxin Cui, Chenglong Zou, Yi Zhong, Zhenhui Dai, Zilin Wang, Kefei Liu, Dunshan Yu, Yuan Wang:
An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. ISCAS 2022: 3468-3472 - [c35]Zilong Shen, Yize Wang, Xing Zhang, Yuan Wang:
A Novel Low-Leakage ESD Power Clamp Circuit with Adjustable Transient Response Time. ISCAS 2022: 3488-3492 - 2021
- [j28]Jiahao Song, Yuan Wang, Minguang Guo, Xiang Ji, Kaili Cheng, Yixuan Hu, Xiyuan Tang, Runsheng Wang, Ru Huang:
TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3377-3387 (2021) - [j27]Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang:
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2655-2659 (2021) - [c34]Jiahao Song, Yuan Wang, Xiyuan Tang, Runsheng Wang, Ru Huang:
A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing. A-SSCC 2021: 1-3 - [c33]Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang:
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. ISCAS 2021: 1-5 - [c32]Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang:
A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. ISCAS 2021: 1-5 - [i3]Yuan Wang, Sebin Gracy, Hideaki Ishii, Karl Henrik Johansson:
Suppressing the endemic equilibrium in SIS epidemics: A state dependent approach. CoRR abs/2106.00122 (2021) - [i2]Qingyu Guo, Yuan Wang, Xiaoxin Cui:
Integer-Only Neural Network Quantization Scheme Based on Shift-Batch-Normalization. CoRR abs/2106.00127 (2021) - 2020
- [j26]Yize Wang, Guangyi Lu, Yuan Wang:
A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. IEEE Access 8: 64730-64738 (2020) - [j25]Yawen Zhang, Runsheng Wang, Xinyue Zhang, Yuan Wang, Ru Huang:
Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators. IEEE Trans. Circuits Syst. 67-II(12): 3387-3391 (2020) - [c31]Yawen Zhang, Sheng Lin, Runsheng Wang, Yanzhi Wang, Yuan Wang, Weikang Qian, Ru Huang:
When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing. DATE 2020: 1287-1290 - [c30]Yawen Zhang, Runsheng Wang, Yixuan Hu, Weikang Qian, Yanzhi Wang, Yuan Wang, Ru Huang:
Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j24]Lizhong Zhang, Yuan Wang, Yize Wang, Xing Zhang, Yandong He:
Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection. Sci. China Inf. Sci. 62(6): 62402:1-62402:8 (2019) - [c29]Xinyue Zhang, Jiahao Song, Yuan Wang, Yawen Zhang, Zuodong Zhang, Runsheng Wang, Ru Huang:
An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ASICON 2019: 1-4 - [c28]Zhao Zhao, Yuan Wang, Xinyue Zhang, Xiaoxin Cui, Ru Huang:
An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training. BioCAS 2019: 1-4 - [c27]Xinyue Zhang, Yuan Wang, Yawen Zhang, Jiahao Song, Zuodong Zhang, Kaili Cheng, Runsheng Wang, Ru Huang:
Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ICICDT 2019: 1-4 - [c26]Zhao Zhao, Yuan Wang, Cheng Li, Xiaoxin Cui, Ru Huang:
A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model. ICICDT 2019: 1-4 - [c25]Weikang Qian, Runsheng Wang, Yuan Wang, Marc D. Riedel, Ru Huang:
A Survey of Computation-Driven Data Encoding. SiPS 2019: 7-12 - [c24]Yawen Zhang, Xinyue Zhang, Jiahao Song, Yuan Wang, Ru Huang, Runsheng Wang:
Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing. SiPS 2019: 19-24 - [i1]Yawen Zhang, Runsheng Wang, Xinyue Zhang, Zherui Zhang, Jiahao Song, Zuodong Zhang, Yuan Wang, Ru Huang:
A Parallel Bitstream Generator for Stochastic Computing. CoRR abs/1904.09554 (2019) - 2018
- [j23]Yuan Wang, Mengyin Jiang, Baoguang Liu, Song Jia, Xing Zhang:
A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process. Int. J. Circuit Theory Appl. 46(8): 1565-1576 (2018) - [c23]Cheng Li, Yuan Wang, Jin Zhang, Xiaoxin Cui, Ru Huang:
A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition. BioCAS 2018: 1-4 - [c22]Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang:
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. ISCAS 2018: 1-5 - [c21]Lu Zhang, Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang:
A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation. ISCAS 2018: 1-4 - 2017
- [j22]Yize Wang, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang:
A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. IEICE Electron. Express 14(9): 20170163 (2017) - [j21]Yuan Wang, Guangyi Lu, Yize Wang, Xing Zhang:
Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. IEICE Trans. Electron. 100-C(3): 344-347 (2017) - [j20]Yuan Wang, Yuequan Liu, Song Jia, Xing Zhang:
Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process. Int. J. Circuit Theory Appl. 45(6): 851-858 (2017) - [c20]Yukuai Chen, Jian Cao, Zhang Qihui, Yuan Wang, Xing Zhang:
A novel equivalent circuit model of the surge wave generator. ASICON 2017: 807-810 - [c19]Guangyi Lu, Yuan Wang, Yize Wang, Xing Zhang:
Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. ISCAS 2017: 1-4 - [c18]Yunfan Yang, Song Jia, Yuan Wang, Shaonan Zhang, Chao Liu:
A reliable true random number generator based on novel chaotic ring oscillator. ISCAS 2017: 1-4 - [c17]Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang:
Compact digital-controlled neuromorphic circuit with low power consumption. ISCAS 2017: 1-4 - 2016
- [j19]Yuan Wang, Guangyi Lu, Haibing Guo, Jian Cao, Song Jia, Xing Zhang:
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. 59(4): 042407:1-042407:9 (2016) - [j18]Jian Cao, Jingya Xu, Yuan Wang, Guangyi Lu, Xing Zhang:
A compact SCR model using advanced BJT models and standard SPICE elements. Sci. China Inf. Sci. 59(10): 109302 (2016) - [j17]Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Xing Zhang:
Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. Sci. China Inf. Sci. 59(12): 122401:1-122401:9 (2016) - [j16]Jian Cao, Yize Wang, Yuan Wang, Guangyi Lu, Xing Zhang:
A novel SPICE circuit model of electrostatic discharge (ESD) generator. IEICE Electron. Express 13(9): 20160238 (2016) - [j15]Guangyi Lu, Yuan Wang, Xing Zhang:
Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. IEICE Trans. Electron. 99-C(5): 590-596 (2016) - [j14]Wenyi Tang, Song Jia, Yuan Wang:
A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis. IEICE Trans. Electron. 99-C(8): 956-962 (2016) - [j13]Yuan Wang, Shanliang Gan, Song Jia, Xing Zhang:
A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology. Int. J. Circuit Theory Appl. 44(9): 1758-1764 (2016) - [j12]Song Jia, Ziyi Wang, Shilin Yan, Yuan Wang:
A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents. Int. J. Circuit Theory Appl. 44(10): 1895-1900 (2016) - [c16]Yuan Wang, Yuequan Liu, Mengyin Jiang, Song Jia, Xing Zhang:
Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics. ISCAS 2016: 1-4 - [c15]Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Xing Zhang:
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. ISCAS 2016: 265-268 - [c14]Song Jia, Ziyi Wang, Zijin Li, Yuan Wang:
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. ISCAS 2016: 2751-2754 - 2015
- [j11]Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Song Jia, Xing Zhang:
Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci. China Inf. Sci. 58(4): 1-9 (2015) - [j10]Yuan Wang, Wei Su, Guangliang Guo, Xing Zhang:
Novel DEM Technique for Current-Steering DAC in 65-nm CMOS Technology. IEICE Trans. Electron. 98-C(12): 1193-1195 (2015) - [c13]Jian Cao, Zhenxu Ye, Yuan Wang, Guangyi Lu, Xing Zhang:
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. ASICON 2015: 1-4 - [c12]Jiyu Chen, Song Jia, Yuan Wang:
A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier. ASICON 2015: 1-4 - [c11]Fangyuan Dang, Yuan Wang, Yuequan Liu, Song Jia, Xing Zhang:
Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. ASICON 2015: 1-4 - [c10]Nan Han, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang:
Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. ASICON 2015: 1-4 - [c9]Song Jia, Weiting Li, Wenyi Tang, Yuan Wang:
A low power and high speed CAM design using pulsed voltage for search-line. ASICON 2015: 1-4 - [c8]Mengyin Jiang, Yuan Wang, Baoguang Liu, Yuequan Liu, Song Jia, Xing Zhang:
A reference-less all-digital burst-mode CDR with embedded TDC. ASICON 2015: 1-4 - [c7]Song Jia, Shilin Yan, Yuan Wang, Ganggang Zhang:
A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. ISCAS 2015: 890-893 - [c6]Yuequan Liu, Yuan Wang, Song Jia, Xing Zhang:
180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance. ISCAS 2015: 1394-1397 - 2014
- [j9]Peng Zhang, Yuan Wang, Xing Zhang, Xiaohua Ma, Yue Hao:
Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp. Sci. China Inf. Sci. 57(2): 1-6 (2014) - 2013
- [j8]Yuan Wang, Baoguang Liu, Wei Su, Junlei Zhao, Xing Zhang:
Thermo data-weighted average dynamic element matching (DEM) encoder for current-steering DACs. IEICE Electron. Express 10(20): 20130459 (2013) - [j7]Song Jia, Li Liu, Xiayu Li, Fengfeng Wu, Yuan Wang, Ganggang Zhang:
Data Convertors Design for Optimization of the DDPL Family. IEICE Trans. Electron. 96-C(9): 1195-1200 (2013) - [j6]Song Jia, Heqing Xu, Fengfeng Wu, Yuan Wang:
A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs. IEICE Trans. Electron. 96-C(9): 1205-1207 (2013) - [j5]Fengfeng Wu, Song Jia, Qinglong Meng, Shigong Lv, Yuan Wang, Dacheng Zhang:
Improved CRC Calculation Strategies for 64-bit Serial RapidIO. IEICE Trans. Electron. 96-C(10): 1330-1338 (2013) - [c5]Baoguang Liu, Yuan Wang, Guangliang Guo, Song Jia, Xing Zhang:
A novel dynamic element match technique in current-steering DAC. ASICON 2013: 1-4 - [c4]Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang:
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. ASICON 2013: 1-4 - [c3]Heqing Xu, Song Jia, Jiyu Chen, Yuan Wang, Gang Du:
A current mode sense amplifier with self-compensation circuit for SRAM application. ASICON 2013: 1-4 - 2012
- [j4]Xiayu Li, Song Jia, Limin Liu, Yuan Wang, Ganggang Zhang:
Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application. Sci. China Inf. Sci. 55(10): 2390-2398 (2012) - [j3]Xiayu Li, Song Jia, Limin Liu, Yuan Wang:
A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF). IEICE Trans. Electron. 95-C(6): 1125-1127 (2012) - 2011
- [j2]Hongyi Li, Yuan Wang, Song Jia, Xing Zhang:
Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM. IEICE Electron. Express 8(24): 2041-2047 (2011) - [c2]Peng Zhang, Yuan Wang, Song Jia, Xing Zhang:
A novel multi-finger layout strategy for GGnMOS ESD protection device. ASICON 2011: 275-278 - 2010
- [j1]Fengfeng Wu, Song Jia, Yuan Wang, Ganggang Zhang:
Low swing drivers based on charge redistribution. Sci. China Inf. Sci. 53(11): 2377-2388 (2010)
2000 – 2009
- 2007
- [c1]Liangguo Shen, Zushu Yan, Xing Zhang, Yuanfu Zhao, Yuan Wang:
Design of High-Performance Voltage Regulators Based on Frequency-Dependent Feedback Factor. ISCAS 2007: 3828-3831
Coauthor Index
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
load content from web.archive.org
Privacy notice: By enabling the option above, your browser will contact the API of web.archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2023-06-05 02:02 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
