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2020 – today
- 2024
[j130]Riccardo Della Sala
, Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo:
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications. IEEE Access 12: 4642-4659 (2024)- 2023
- [j129]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Very-Low-Voltage Charge Pump Topologies for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2283-2292 (2023) - [c159]Javier Beloso-Legarra, Antonio Lopez-Martin, Carlos Aristoteles De la Cruz, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
GBW Optimization in Two-Stage OTAs Operating in Weak Inversion. DCIS 2023: 1-4 - [c158]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Fully On-Chip Charge Pump-based Boost Converter in 65-nm CMOS for Single Solar Cell Powered IC. ISCAS 2023: 1-5 - [c157]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Triple Clock Boosted Voltage Multiplier: A Design Strategy to Heavily Reduce Rise Time. NEWCAS 2023: 1-5 - [c156]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
An Energy-Efficient Design Strategy for Dickson Charge Pumps with Linear Distributed Capacitance. NEWCAS 2023: 1-5 - 2022
- [j128]Hamed Aminzadeh, Alfio Dario Grasso, Gaetano Palumbo:
A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers. IEEE Access 10: 14062-14075 (2022) - [j127]Federico Nicolas Guerrero, Enrique Mario Spinelli, Alfio Dario Grasso, Gaetano Palumbo:
Double-Differential Amplifier for sEMG Measurement by Means of a Current-Mode Approach. IEEE Access 10: 45870-45880 (2022) - [j126]Gianluca Giustolisi, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders. IEEE Access 10: 75482-75494 (2022) - [j125]Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo, Giuseppe Scotti:
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers. IEEE Access 10: 99702-99708 (2022) - [j124]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa:
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers. IEEE Access 10: 118082-118092 (2022) - [j123]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review. Int. J. Circuit Theory Appl. 50(5): 1462-1486 (2022) - [j122]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
The Dickson Charge Pump as a Signal Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 69(9): 3476-3489 (2022) - [j121]Javier Beloso-Legarra, Alfio Dario Grasso, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Pennisi:
Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3154-3158 (2022) - [j120]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4128-4132 (2022) - 2021
- [j119]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes. IEEE Access 9: 41958-41964 (2021) - [j118]Gianluca Giustolisi, Gaetano Palumbo:
Design of CMOS three-stage amplifiers for near-to-minimum settling-time. Microelectron. J. 107: 104939 (2021) - [j117]Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 680-691 (2021) - [j116]Gianluca Giustolisi, Gaetano Palumbo:
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 998-1011 (2021) - [j115]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa:
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2895-2901 (2021) - [j114]Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo:
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 998-1008 (2021) - [c155]Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML. ISCAS 2021: 1-5 - [c154]Gianluca Giustolisi, Gaetano Palumbo:
Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints. ISCAS 2021: 1-5 - [c153]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Comparison of the Wide-Frequency Range Dynamic Behavior of the Dickson and Cockcroft-Walton Voltage Multipliers. MWSCAS 2021: 348-351 - [c152]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Dickson Charge Pump: Design Strategy for Optimum Efficiency. NEWCAS 2021: 1-4 - 2020
- [j113]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start. IEEE Access 8: 188959-188969 (2020) - [j112]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A simple and effective design strategy to increase power conversion efficiency of linear charge pumps. Int. J. Circuit Theory Appl. 48(2): 157-161 (2020) - [j111]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa:
Linear distribution of capacitance in Dickson charge pumps to reduce rise time. Int. J. Circuit Theory Appl. 48(4): 555-566 (2020) - [j110]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Current-mode body-biased switch to increase performance of linear charge pumps. Int. J. Circuit Theory Appl. 48(11): 1864-1872 (2020) - [j109]Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
Delay models and design guidelines for MCML gates with resistor or PMOS load. Microelectron. J. 99: 104755 (2020) - [j108]Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 560-564 (2020) - [j107]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A High-Performance Charge Pump Topology for Very-Low-Voltage Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1304-1308 (2020) - [j106]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging. IEEE Trans. Circuits Syst. 67-II(12): 3312-3316 (2020) - [j105]Gaetano Palumbo, Giuseppe Scotti:
A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS. IEEE Trans. Circuits Syst. 67-I(12): 4696-4706 (2020)
2010 – 2019
- 2019
- [j104]Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi:
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies. Microelectron. J. 92 (2019) - [j103]Andrea Ballo, Alfio Dario Grasso, Gianluca Giustolisi, Gaetano Palumbo:
Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1977-1981 (2019) - [j102]Gianluca Giustolisi, Gaetano Palumbo:
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4557-4570 (2019) - 2018
- [j101]Gianluca Giustolisi, Gaetano Palumbo:
Bessel-like compensation of three-stage operational transconductance amplifiers. Int. J. Circuit Theory Appl. 46(4): 729-747 (2018) - [j100]Giulia Di Capua, Nuno Horta, Francisco V. Fernández, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi:
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017. Integr. 63: 273-274 (2018) - [j99]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Switched-Capacitor Power Management Integrated Circuit for Autonomous Internet of Things Node. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1455-1459 (2018) - [j98]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of CL. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1529-1533 (2018) - [j97]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Dual Push-Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1879-1883 (2018) - [c151]Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering. ICECS 2018: 233-236 - [c150]Gianluca Giustolisi, Gaetano Palumbo:
Design of CMOS OTAs with Settling-Time Constraints. ICECS 2018: 505-508 - [c149]Andrea Ballo, Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo:
A Clock Boosted Charge Pump with Reduced Rise Time. ICECS 2018: 605-608 - [c148]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Davide Marano:
Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW. ICICDT 2018: 37-40 - [c147]Gianluca Giustolisi, Gaetano Palumbo:
Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads. ISCAS 2018: 1-4 - [c146]Gianluca Giustolisi, Gaetano Palumbo:
Settling-time oriented OTA design through the approximation of the ideal delay. ISCAS 2018: 1-4 - [c145]Davide Bellizia, Gaetano Palumbo, Giuseppe Scotti, Alessandro Trifiletti:
A Novel Very Low Voltage Topology to implement MCML XOR Gates. PRIME 2018: 157-160 - 2017
- [j96]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Willy Sansen:
The noise performance of CMOS Miller operational transconductance amplifiers with embedded current-buffer frequency compensation. Int. J. Circuit Theory Appl. 45(4): 457-465 (2017) - [j95]Gianluca Giustolisi, Gaetano Palumbo:
Robust design of CMOS amplifiers oriented to settling-time specification. Int. J. Circuit Theory Appl. 45(10): 1329-1348 (2017) - [j94]Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo:
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3509-3520 (2017) - 2016
- [j93]Davide Marano, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1349-1359 (2016) - [c144]Davide Marano, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
A 0.003-mm2 50-mW three-stage amplifier driving 10-nF with 2.7-MHz GBW. ICECS 2016: 728-731 - [c143]Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo:
Verilog-a modeling of Silicon Photo-Multipliers. ISCAS 2016: 1270-1273 - 2015
- [j92]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 835-843 (2015) - [j91]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1453-1462 (2015) - [j90]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2035-2043 (2015) - [j89]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2476-2484 (2015) - [j88]Gianluca Giustolisi, Gaetano Palumbo:
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(11): 2641-2651 (2015) - [j87]Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo:
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes. IEEE Trans. Instrum. Meas. 64(1): 271-277 (2015) - [c142]Massimo Alioto, Gaetano Palumbo, Elio Consoli:
PVT variations in differential flip-flops: A comparative analysis. ECCTD 2015: 1-4 - [c141]Giuseppe Di Cataldo, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Single-miller all-passive compensation network for three-stage OTAs. ECCTD 2015: 1-4 - [c140]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
195-nW 120-dB subthreshold CMOS OTA driving up to 200 pF and occupying only 4.4-10-3 mm2. ICECS 2015: 65-68 - [c139]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Comparative analysis of the robustness of master-slave flip-flops against variations. ICECS 2015: 117-120 - [c138]Massimo Alioto, Gaetano Palumbo, Elio Consoli:
Variability budgetin pulsed flip-flops. NEWCAS 2015: 1-4 - [c137]Davide Marano, Giovanni Bonanno, S. Garozzo, Giuseppe Romeo, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
A new enhanced PSPICE implementation of the equivalent circuit model of SiPM detectors. NEWCAS 2015: 1-4 - 2014
- [j86]Alfio Dario Grasso, Davide Marano, Fermin Esparza-Alfaro, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Pennisi:
Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 663-670 (2014) - [j85]Fermin Esparza-Alfaro, Salvatore Pennisi, Gaetano Palumbo, Antonio J. López-Martín:
Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 574-578 (2014) - [j84]Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto:
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1593-1605 (2014) - [c136]Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo:
Monolithic quenching-and-reset circuit for single-photon avalanche diodes. ICECS 2014: 76-79 - [c135]Fermin Esparza-Alfaro, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Permisi:
CMOS class-AB tunable voltage-feedback current operational amplifier. ICECS 2014: 140-143 - [c134]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Giuseppe Di Cataldo:
High-performance frequency compensation topology for four-stage OTAs. ICECS 2014: 211-214 - [c133]Davide Marano, Giovanni Bonanno, Massimiliano Belluso, Sergio Billotta, Alessandro Grillo, S. Garozzo, Giuseppe Romeo, Alfio Dario Grasso, Salvatore Pennisi, Gaetano Palumbo:
A new accurate analytical expression for the SiPM transient response to single photons. ICECS 2014: 514-517 - 2013
- [c132]Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo:
A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers. ECCTD 2013: 1-4 - [c131]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Optimized frequency compensation topology for low-power three-stage OTAs. ECCTD 2013: 1-4 - 2012
- [j83]Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo:
Behavioral modeling of statistical phenomena of single-photon avalanche diodes. Int. J. Circuit Theory Appl. 40(7): 661-679 (2012) - [j82]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
From energy-delay metrics to constraints on the design of digital circuits. Int. J. Circuit Theory Appl. 40(8): 815-834 (2012) - [j81]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 159-169 (2012) - [j80]Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale:
Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1880-1893 (2012) - [j79]Gaetano Palumbo, Melita Pennisi, Massimo Alioto:
A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2292-2300 (2012) - [j78]Elio Consoli, Gaetano Palumbo, Melita Pennisi:
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 284-295 (2012) - [c130]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
A simple keeper topology to reduce delay variations in nanometer domino logic. ISCAS 2012: 1576-1579 - [c129]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
Logic gates dynamic modeling by means of an ultra-compact MOS model. ISCAS 2012: 3250-3253 - [c128]Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey:
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. ISSCC 2012: 482-484 - 2011
- [j77]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Optimized design of parallel carry-select adders. Integr. 44(1): 62-74 (2011) - [j76]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 725-736 (2011) - [j75]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 737-750 (2011) - [c127]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model. ECCTD 2011: 512-515 - [c126]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
An ultra-compact MOS model in nanometer technologies. ECCTD 2011: 520-523 - [c125]Gaetano Palumbo, Melita Pennisi, Ramón González Carvajal:
Figures of merit for class AB input stages. ECCTD 2011: 749-752 - [c124]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications. ISCAS 2011: 29-32 - [c123]Elio Consoli, Gaetano Palumbo, Melita Pennisi:
TG Master-Slave FFs: High-speed optimization. ISCAS 2011: 554-557 - [c122]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
DET FF topologies: A detailed investigation in the energy-delay-area domain. ISCAS 2011: 563-566 - [c121]Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo:
Verilog-A modeling of SPAD statistical phenomena. ISCAS 2011: 773-776 - 2010
- [j74]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads. IET Circuits Devices Syst. 4(2): 87-98 (2010) - [j73]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Analytical comparison of reversed nested Miller frequency compensation techniques. Int. J. Circuit Theory Appl. 38(7): 709-737 (2010) - [j72]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Simple and accurate modeling of the output transition time in nanometer CMOS gates. Int. J. Circuit Theory Appl. 38(10): 995-1012 (2010) - [j71]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications. J. Circuits Syst. Comput. 19(2): 325-334 (2010) - [j70]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1273-1286 (2010) - [j69]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1583-1596 (2010) - [j68]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 697-710 (2010) - [c120]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. ISCAS 2010: 321-324 - [c119]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs. ISCAS 2010: 777-780 - [c118]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers. ISCAS 2010: 2816-2819 - [c117]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers. ISCAS 2010: 2832-2835 - [c116]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. PATMOS 2010: 62-72
2000 – 2009
- 2009
- [j67]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
Approach to analyse and design nearly sinusoidal oscillators. IET Circuits Devices Syst. 3(4): 204-221 (2009) - [j66]Rosario Mita, Gaetano Palumbo:
Propagation delay of an RC-circuit with a ramp input: An analytical very accurate and simple model. Int. J. Circuit Theory Appl. 37(9): 987-994 (2009) - [j65]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Improved Power-Efficient RNMC Technique with voltage Buffer and Nulling resistors for Low-Power High-Load Three-Stage amplifiers. J. Circuits Syst. Comput. 18(7): 1321-1331 (2009) - [j64]