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2020 – today
- 2024
[j27]Eunji Kwon
, Jongho Yoon, Seokhyeong Kang:
Mobile Transformer Accelerator Exploiting Various Line Sparsity and Tile-Based Dynamic Quantization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1808-1821 (2024)- [j26]Youngchang Choi, Sejin Park, Minjeong Choi, Kyongsu Lee, Seokhyeong Kang:
MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors. IEEE Trans. Circuits Syst. I Regul. Pap. 71(5): 2045-2056 (2024) - [c77]Andrew B. Kahng, Seokhyeong Kang, Minhyuk Kweon:
Improvement of Mixed Track - Height Standard-Cell Placement. DATE 2024: 1-6 - [c76]Seungju Lee, Kyumin Cho, Eunji Kwon, Sejin Park, Seojeong Kim, Seokhyeong Kang:
ViT- ToGo: Vision Transformer Accelerator with Grouped Token Pruning. DATE 2024: 1-6 - [c75]Ho-Jin Lee, Kyeong-Jun Lee, Youngchang Choi, Kyongsu Lee, Seokhyeong Kang, Jae-Yoon Sim:
Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation. DATE 2024: 1-2 - [c74]Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang:
CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning. DATE 2024: 1-6 - [c73]Jaemin Seo, Sejin Park, Seokhyeong Kang:
Unveiling the Black-Box: Leveraging Explainable AI for FPGA Design Space Optimization. DATE 2024: 1-6 - [c72]Seongbin Kwon, Dohun Kim, Sunghye Park, Seojeong Kim, Seokhyeong Kang:
QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization. ISQED 2024: 1-7 - [c71]Donggyu Kim, Minjae Kim, Junseok Hur, Jakang Lee, Jinoh Cho, Seokhyeong Kang:
TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path. MLCAD 2024: 19:1-19:7 - 2023
- [j25]Daeyeon Kim, Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang:
Construction of Realistic Place-and-Route Benchmarks for Machine Learning Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 2030-2042 (2023) - [j24]Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang:
Optimizing Ternary Multiplier Design With Fast Ternary Adder. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 766-770 (2023) - [c70]Jaekyung Im, Seokhyeong Kang:
Graph Partitioning Approach for Fast Quantum Circuit Simulation. ASP-DAC 2023: 690-695 - [c69]Minjeong Choi, Youngchang Choi, Kyongsu Lee, Seokhyeong Kang:
Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing. DAC 2023: 1-6 - [c68]Youngchang Choi, Minjeong Choi, Kyongsu Lee, Seokhyeong Kang:
MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors. DATE 2023: 1-5 - [c67]Daeyeon Kim, Jakang Lee, Seokhyeong Kang:
Routability Prediction using Deep Hierarchical Classification and Regression. DATE 2023: 1-2 - [c66]Eunji Kwon, Haena Song, Jihye Park, Seokhyeong Kang:
Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines, and Blocks in Transformers in Computer Vision. DATE 2023: 1-6 - [c65]Sung-Yun Lee, Seonghyeon Park, Daeyeon Kim, Minjae Kim, Tuyen Pham Le, Seokhyeong Kang:
RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization. DATE 2023: 1-6 - [c64]Haena Song, Jongho Yoon, Dohun Kim, Eunji Kwon, Tae-Hyun Oh, Seokhyeong Kang:
FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks. DATE 2023: 1-6 - [c63]Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang:
ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks. ICCAD 2023: 1-9 - [c62]Seonghyeon Park, Daeyeon Kim, Seongbin Kwon, Seokhyeong Kang:
Routability Prediction and Optimization Using Explainable AI. ICCAD 2023: 1-8 - [c61]Jakang Lee, Jaeseung Lee, Seonghyeon Park, Seokhyeong Kang:
Multi-Source Transfer Learning for Design Technology Co-Optimization. ISLPED 2023: 1-6 - [c60]Sejin Park, Youngchang Choi, Seokhyeong Kang:
Soft Actor-Critic Reinforcement Learning-Based Optimization for Analog Circuit Sizing. ISOCC 2023: 47-48 - [c59]Junseok Hur, Jaekyung Im, Seokhyeong Kang:
Placement Initialization via Community Detection. ISOCC 2023: 125-126 - [c58]Donggyu Kim, Jakang Lee, Seokhyeong Kang:
Advanced Parasitic Capacitance Extraction using Active Learning. ISOCC 2023: 349-350 - [c57]Jaeseung Lee, Sejin Park, Minhyeok Kweon, Seokhyeong Kang:
Machine Learning-based Fast Circuit Simulation for Analog Circuit Array. MLCAD 2023: 1-6 - [c56]Seonghyeon Park, Daeyeon Kim, Seokhyeong Kang:
Invited: Acceleration on Physical Design: Machine Learning-based Routability Optimization. SLIP 2023: 5:1-5:6 - [i2]Ludwig Schmid, Sunghye Park, Seokhyeong Kang, Robert Wille:
Hybrid Circuit Mapping: Leveraging the Full Spectrum of Computational Capabilities of Neutral Atom Quantum Computers. CoRR abs/2311.14164 (2023) - 2022
- [j23]Kiseo Kang, Donggyu Minn, Seongun Bae, Jaeho Lee, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Jae-Yoon Sim:
A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit. IEEE J. Solid State Circuits 57(11): 3274-3287 (2022) - [j22]Jieun Lee, Kim Sung-Bin, Seokhyeong Kang, Tae-Hyun Oh:
Lightweight Speaker Recognition in Poincaré Spaces. IEEE Signal Process. Lett. 29: 224-228 (2022) - [j21]Hyeokjun Kwon, Younghoon Byun, Seokhyeong Kang, Youngjoo Lee:
CHAMP: Channel Merging Process for Cost-Efficient Highly-Pruned CNN Acceleration. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3308-3319 (2022) - [c55]Aeri Kim, Seungju Lee, Eunji Kwon, Seokhyeong Kang:
Adaptive FSP: Adaptive Architecture Search with Filter Shape Pruning. ACCV (1) 2022: 539-555 - [c54]Sung-Yun Lee, Daeyeon Kim, Kyungjun Min, Seokhyeong Kang:
Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration. ASP-DAC 2022: 178-183 - [c53]Sunghye Park, Daeyeon Kim, Minhyuk Kweon, Jae-Yoon Sim, Seokhyeong Kang:
A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers. DAC 2022: 13-18 - [c52]Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee:
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. DATE 2022: 1077-1082 - [c51]Myong Kong, Daeyeon Kim, Minhyuk Kweon, Seokhyeong Kang:
GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN. ACM Great Lakes Symposium on VLSI 2022: 177-181 - [c50]Sunghye Park, Dohun Kim, Jae-Yoon Sim, Seokhyeong Kang:
MCQA: Multi-Constraint Qubit Allocation for Near-FTQC Device. ICCAD 2022: 108:1-108:9 - [c49]Jihye Park, Seokhyeong Kang:
CPR: Crossbar-grain Pruning for an RRAM-based Accelerator with Coordinate-based Weight Mapping. ICCD 2022: 336-343 - [c48]Kiseo Kang, Donggyu Minn, Seunghun Bae, Jaeho Lee, Seongun Bae, Gichang Jung, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Jae-Yoon Sim:
A Cryo-CMOS Controller IC With Fully Integrated Frequency Generators for Superconducting Qubits. ISSCC 2022: 362-364 - 2021
- [j20]Sangho Yoon, Chanhee Lee, Ho Sub Lee, Young Hwan Kim, Seokhyeong Kang:
Fluctuation-Based Fade Detection for Local Scene Changes. IEEE Access 9: 149732-149743 (2021) - [j19]Hyun-jeong Kwon, Daeyeon Kim, Young Hwan Kim, Seokhyeong Kang:
Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based Sensitivity Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1567-1577 (2021) - [j18]Eunji Kwon, Sodam Han, Yoonho Park, Jongho Yoon, Seokhyeong Kang:
Reinforcement Learning-Based Power Management Policy for Mobile Device Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4156-4169 (2021) - [j17]Sunmean Kim, Yesung Kang, Seunghan Baek, Youngchang Choi, Seokhyeong Kang:
Low-Power Ternary Multiplication Using Approximate Computing. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2947-2951 (2021) - [j16]Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Bangqi Xu:
Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 591-604 (2021) - [c47]Sunghoon Kim, Hyun-jeong Kwon, Eunji Kwon, Youngchang Choi, Tae-Hyun Oh, Seokhyeong Kang:
MDARTS: Multi-objective Differentiable Neural Architecture Search. DATE 2021: 1344-1349 - [c46]Yesung Kang, Eunji Kwon, Seunggyu Lee, Younghoon Byun, Youngjoo Lee, Seokhyeong Kang:
Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks. DATE 2021: 1516-1521 - [c45]Daeyeon Kim, Hyun-jeong Kwon, Sung-Yun Lee, Seungwon Kim, Mingyu Woo, Seokhyeong Kang:
Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator. DATE 2021: 1809-1814 - [c44]Youngchang Choi, Sunmean Kim, Kyongsu Lee, Seokhyeong Kang:
Design and Analysis of a Low-Power Ternary SRAM. ISCAS 2021: 1-4 - [c43]Jaekyung Im, Seokhyeong Kang:
Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification. ISOCC 2021: 59-60 - [c42]Jiyoung Min, Sunmean Kim, Seokhyeong Kang:
Memcapacitor based Minimum and Maximum Gate Design. ISOCC 2021: 75-76 - [c41]Seunggyu Lee, Jongho Yoon, Jakang Lee, Seokhyeong Kang:
Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM. ISOCC 2021: 109-110 - [c40]Aeri Kim, Seokhyeong Kang:
Data Protection Method for Flash Memory in Serial Peripheral Interface. ISOCC 2021: 117-118 - [c39]Minjeong Choi, Youngchang Choi, Sunmean Kim, Seokhyeong Kang:
Ternary Sense Amplifier Design for Ternary SRAM. ISOCC 2021: 151-152 - [c38]Chanhee Lee, Sangho Yoon, Seokhyeong Kang:
Components Analysis on Audio Signal Mixtures. ISOCC 2021: 363-364 - [c37]Kiseo Kang, ByungJun Kim, Gahyun Choi, Sun-Kyung Lee, Jisoo Choi, Jaeho Lee, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Yonuk Chong, Jae-Yoon Sim:
A 5.5mW/Channel 2-to-7 GHz Frequency Synthesizable Qubit-Controlling Cryogenic Pulse Modulator for Scalable Quantum Computers. VLSI Circuits 2021: 1-2 - [i1]Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee:
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. CoRR abs/2111.07584 (2021) - 2020
- [j15]Sodam Han, Yonghee Yun, Young Hwan Kim, Seokhyeong Kang:
Proactive Scenario Characteristic-Aware Online Power Management on Mobile Systems. IEEE Access 8: 69695-69711 (2020) - [j14]Daeyeon Kim, SangGi Do, Sung-Yun Lee, Seokhyeong Kang:
Compact Topology-Aware Bus Routing for Design Regularity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1744-1749 (2020) - [j13]Hyun-jeong Kwon, Sung-Yun Lee, Young Hwan Kim, Seokhyeong Kang:
Additive Statistical Leakage Analysis Using Exponential Mixture Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4985-4998 (2020) - [j12]Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang:
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3138-3151 (2020) - [c36]Eunji Kwon, Sodam Han, Yoonho Park, Young Hwan Kim, Seokhyeong Kang:
Late Breaking Results: Reinforcement Learning-based Power Management Policy for Mobile Device Systems. DAC 2020: 1-2 - [c35]Yesung Kang, Yoonho Park, Sunghoon Kim, Eunji Kwon, Taeho Lim, Sangyun Oh, Mingyu Woo, Seokhyeong Kang:
Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling. DATE 2020: 1091-1096 - [c34]Yoonho Park, Yesung Kang, Sunghoon Kim, Eunji Kwon, Seokhyeong Kang:
GRLC: grid-based run-length compression for energy-efficient CNN accelerator. ISLPED 2020: 91-96 - [c33]Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, Byoung Hun Lee:
Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. ISMVL 2020: 155-158 - [c32]Seunghan Baek, Sunmean Kim, Youngchang Choi, Seokhyeong Kang:
MTCMOS-based Ternary to Binary Converter. ISOCC 2020: 5-6 - [c31]Youngchang Choi, Sunmean Kim, Seunghan Baek, Seokhyeong Kang:
Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion. ISOCC 2020: 254-255
2010 – 2019
- 2019
- [j11]Seungwon Kim, Ki Jin Han, Youngmin Kim, Seokhyeong Kang:
Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems. IEEE Access 7: 95305-95313 (2019) - [j10]Ho Sub Lee, Gyu Jin Bae, Sung In Cho, Young Hwan Kim, Seokhyeong Kang:
SmartGrid: Video Retargeting With Spatiotemporal Grid Optimization. IEEE Access 7: 127564-127579 (2019) - [c30]Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Kambiz Samadi, Bangqi Xu:
Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology. DATE 2019: 842-847 - [c29]SangGi Do, Mingyu Woo, Seokhyeong Kang:
Fence-Region-Aware Mixed-Height Standard Cell Legalization. ACM Great Lakes Symposium on VLSI 2019: 259-262 - [c28]Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang:
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. ISMVL 2019: 37-42 - [c27]Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang:
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm. ISMVL 2019: 158-163 - [c26]Sunghye Park, Sunmean Kim, Seokhyeong Kang:
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU. ISOCC 2019: 25-26 - [c25]Eunji Kwon, Yesung Kang, Seokhyeong Kang:
Outlier-aware Time-multiplexing MAC for Higher Energy-Efficiency on CNNs. ISOCC 2019: 119-120 - 2018
- [j9]Hyun-jeong Kwon, Mingyu Woo, Young Hwan Kim, Seokhyeong Kang:
Statistical Leakage Analysis Using Gaussian Mixture Model. IEEE Access 6: 51939-51950 (2018) - [j8]Hyun-jeong Kwon, Jae Hoon Kim, Seokhyeong Kang, Young Hwan Kim:
SoftCorner: Relaxation of Corner Values for Deterministic Static Timing Analysis of VLSI Systems. IEEE Access 6: 60115-60127 (2018) - [c24]Sunmean Kim, Taeho Lim, Seokhyeong Kang:
An optimal gate design for the synthesis of ternary logic circuits. ASP-DAC 2018: 476-481 - [c23]Seungwon Kim, Ki Jin Han, Youngmin Kim, Seokhyeong Kang:
Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study. DATE 2018: 885-888 - [c22]Hyun-jeong Kwon, Young Hwan Kim, Seokhyeong Kang:
Estimation of Leakage Distribution Utilizing Gaussian Mixture Model. ISOCC 2018: 149-150 - 2017
- [c21]Seungwon Kim, SangGi Do, Seokhyeong Kang:
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization. DAC 2017: 55:1-55:6 - [c20]Mingyu Woo, Seungwon Kim, Seokhyeong Kang:
GRASP based metaheuristics for layout pattern classification. ICCAD 2017: 512-518 - [c19]Yesung Kang, Jaewoo Kim, Sunmin Kim, Sunhae Shin, E-San Jang, Jae Won Jeong, Kyung Rok Kim, Seokhyeong Kang:
A Novel Ternary Multiplier Based on Ternary CMOS Compact Model. ISMVL 2017: 25-30 - 2016
- [j7]Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, Youngsoo Shin:
Wakeup scheduling and its buffered tree synthesis for power gating circuits. Integr. 53: 157-170 (2016) - [j6]Seungwon Kim, Seokhyeong Kang, Ki Jin Han, Youngmin Kim:
Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC. ACM Trans. Design Autom. Electr. Syst. 21(3): 44:1-44:19 (2016) - [j5]Sangmin Kim, Seokhyeong Kang, Youngsoo Shin:
Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization. ACM Trans. Design Autom. Electr. Syst. 21(3): 51:1-51:23 (2016) - [c18]Yesung Kang, Jaewoo Kim, Seokhyeong Kang:
Novel approximate synthesis flow for energy-efficient FIR filter. ICCD 2016: 96-102 - [c17]SangGi Do, Seungwon Kim, Seokhyeong Kang:
Skew control methodology for useful-skew implementation. ISOCC 2016: 221-222 - 2015
- [j4]Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez:
An Improved Methodology for Resilient Design Implementation. ACM Trans. Design Autom. Electr. Syst. 20(4): 66:1-66:26 (2015) - [c16]Jaemin Lee, Seungwon Kim, Youngmin Kim, Seokhyeong Kang:
An optimal operating point by using error monitoring circuits with an error-resilient technique. VLSI-SoC 2015: 69-73 - 2014
- [c15]Andrew B. Kahng, Seokhyeong Kang, Jiajia Li:
A new methodology for reduced cost of resilience. ACM Great Lakes Symposium on VLSI 2014: 157-162 - 2013
- [b1]Seokhyeong Kang:
Low-Power Integrated-Circuit Implementation Exploiting System and Application Information /. University of California, San Diego, USA, 2013 - [j3]Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong:
Many-Core Token-Based Adaptive Power Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1288-1292 (2013) - [j2]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Enhancing the Efficiency of Energy-Constrained DVFS Designs. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1769-1782 (2013) - [c14]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee:
Smart non-default routing for clock power reduction. DAC 2013: 91:1-91:7 - [c13]Andrew B. Kahng, Seokhyeong Kang, Bongil Park:
Active-mode leakage reduction with data-retained power gating. DATE 2013: 1209-1214 - [c12]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar:
High-performance gate sizing with a signoff timer. ICCAD 2013: 450-457 - [c11]Wei-Ting Jonas Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Statistical analysis and modeling for error composition in approximate computation circuits. ICCD 2013: 47-53 - [c10]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani:
Learning-based approximation of interconnect delay and slew in signoff timing tools. SLIP 2013: 1-8 - 2012
- [j1]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 404-417 (2012) - [c9]Andrew B. Kahng, Seokhyeong Kang:
Accuracy-configurable adder for approximate arithmetic designs. DAC 2012: 820-825 - [c8]Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong:
MAPG: Memory access power gating. DATE 2012: 1054-1059 - [c7]Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov:
Sensitivity-guided metaheuristics for accurate discrete gate sizing. ICCAD 2012: 233-239 - [c6]Andrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong:
TAP: token-based adaptive power gating. ISLPED 2012: 203-208 - [c5]Andrew B. Kahng, Seokhyeong Kang:
Construction of realistic gate sizing benchmarks with known optimal solutions. ISPD 2012: 153-160 - 2010
- [c4]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Slack redistribution for graceful degradation under voltage overscaling. ASP-DAC 2010: 825-831 - [c3]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Recovery-driven design: a power minimization methodology for error-tolerant processor modules. DAC 2010: 825-830 - [c2]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Designing a processor from the ground up to allow voltage/reliability tradeoffs. HPCA 2010: 1-11 - [c1]Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang:
Toward effective utilization of timing exceptions in design optimization. ISQED 2010: 54-61
Coauthor Index
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