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"A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS."
Xiangyu Meng et al. (2021)
- Xiangyu Meng, Weihao Kong, Haifeng Yang, Yecong Li, Xuan Li:
A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS. ISCAS 2021: 1-4
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