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"67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process."

Chua-Chin Wang, Chien-Ping Kuo (2021)

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DOI: 10.1109/ISCAS51556.2021.9401099

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-02

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  dblp key:
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Chua-Chin Wang, Chien-Ping Kuo:
67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process. ISCAS 2021: 1-4

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