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Juinn-Dar Huang
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2020 – today
- 2024
- [j25]Moi Hoon Yap
, Bill Cassidy, Michal Byra, Ting-Yu Liao, Huahui Yi, Adrian Galdran, Yung-Han Chen, Raphael Brüngel, Sven Koitka, Christoph M. Friedrich
, Yu-Wen Lo, Ching-Hui Yang, Kang Li, Qicheng Lao, Miguel Ángel González Ballester, Gustavo Carneiro, Yi-Jen Ju, Juinn-Dar Huang, Joseph M. Pappachan
, Neil D. Reeves, Vishnu Chandrabalan, Darren Dancey, Connah Kendrick:
Diabetic foot ulcers segmentation challenge report: Benchmark and analysis. Medical Image Anal. 94: 103153 (2024) - [c61]Yu-Da Chu, Pei-Hsuan Kuo, Lyu-Ming Ho, Juinn-Dar Huang:
A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems. AICAS 2024: 437-441 - [c60]Yi-Zeng Fang, Lung-Hao Lee, Juinn-Dar Huang:
NYCU-NLP at EXIST 2024: Leveraging Transformers with Diverse Annotations for Sexism Identification in Social Networks. CLEF (Working Notes) 2024: 1003-1011 - [c59]Meng-Hsun Hsieh, Xuan-Hong Li, Yu-Hsiang Huang, Pei-Hsuan Kuo, Juinn-Dar Huang:
A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications. ISCAS 2024: 1-5 - 2023
- [j24]Ling-Yen Song
, Chih-Yun Chou
, Tung-Chieh Kuo
, Chien-Nan Liu
, Juinn-Dar Huang
:
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. ACM Trans. Design Autom. Electr. Syst. 28(2): 18:1-18:22 (2023) - [c58]Yu-Hsiang Huang, Pei-Hsuan Kuo, Juinn-Dar Huang
:
Hardware-Friendly Activation Function Designs and Its Efficient VLSI Implementations for Transformer-Based Applications. AICAS 2023: 1-5 - [c57]Pei-Hsuan Kuo, Yu-Hsiang Huang, Juinn-Dar Huang
:
Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning. AICAS 2023: 1-5 - [c56]Shan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang
:
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis. VLSI-SoC 2023: 1-6 - 2022
- [c55]Chia-Heng Hu, I-Hao Tseng, Pei-Hsuan Kuo, Juinn-Dar Huang
:
An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability. AICAS 2022: 246-249 - [c54]Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang
:
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. ASP-DAC 2022: 80-85 - [c53]Yung-Han Chen
, Yi-Jen Ju, Juinn-Dar Huang
:
Capture the Devil in the Details via Partition-then-Ensemble on Higher Resolution Images. DFUC@MICCAI 2022: 52-64 - [c52]Wei-Cheng Chou, Cheng-Wei Huang, Juinn-Dar Huang
:
Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets. VLSI-DAT 2022: 1-4 - [c51]Kang-Yi Fan, Jyun-Hua Chen, Chien-Nan Liu, Juinn-Dar Huang
:
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. VLSI-DAT 2022: 1-4 - 2021
- [j23]Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin
, Yung-Chih Chen, Juinn-Dar Huang
, Chun-Yao Wang:
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. ACM J. Emerg. Technol. Comput. Syst. 17(2): 15:1-15:23 (2021) - [c50]Wei-Chen Lin, Ya-Chu Chang, Juinn-Dar Huang
:
An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing. AICAS 2021: 1-5 - [c49]Shuaijie Ying, Sudip Roy, Juinn-Dar Huang
, Shigeru Yamashita:
Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip. DSD 2021: 488-494 - [c48]Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu, Juinn-Dar Huang
:
Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips. VLSI-DAT 2021: 1-4 - [i1]Cheng-Wei Huang, Tim-Wei Chen, Juinn-Dar Huang:
All-You-Can-Fit 8-Bit Flexible Floating-Point Format for Accurate and Memory-Efficient Inference of Deep Neural Networks. CoRR abs/2104.07329 (2021) - 2020
- [j22]Sukanta Bhattacharjee
, Robert Wille
, Juinn-Dar Huang
, Bhargab B. Bhattacharya:
Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 816-829 (2020) - [c47]Yi Lu, Yi-Lin Wu, Juinn-Dar Huang
:
A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization. AICAS 2020: 198-202 - [c46]Yi-Lin Wu, Yi Lu, Juinn-Dar Huang
:
High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j21]Ankur Gupta
, Juinn-Dar Huang
, Shigeru Yamashita, Sudip Roy:
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips. ACM Trans. Design Autom. Electr. Syst. 24(2): 21:1-21:24 (2019) - [c45]Ling-Yen Song, Yi-Ling Chen, Yung-Chun Lei, Juinn-Dar Huang
:
Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs. ICCD 2019: 422-428 - [c44]Ling-Yen Song, Yu-Ying Li, Yung-Chun Lei, Juinn-Dar Huang
:
Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips. ISVLSI 2019: 425-430 - [c43]Kang-Yi Fan, Shigeru Yamashita, Juinn-Dar Huang
:
Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models. VLSI-DAT 2019: 1-4 - 2018
- [j20]Sukanta Bhattacharjee
, Yi-Ling Chen, Juinn-Dar Huang
, Bhargab B. Bhattacharya:
Concentration-Resilient Mixture Preparation with Digital Microfluidic Lab-on-Chip. ACM Trans. Embed. Comput. Syst. 17(2): 49:1-49:12 (2018) - [c42]Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang
, Bhargab B. Bhattacharya:
Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip. DATE 2018: 1399-1404 - [c41]Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang
, Chun-Yao Wang:
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. ISVLSI 2018: 257-262 - [c40]Yung-Chun Lei, Tien-Kuo Lin, Juinn-Dar Huang
:
Multi-target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips. ISVLSI 2018: 655-659 - [c39]Chun-Yu Lin, Juinn-Dar Huang
, Hailong Yao, Tsung-Yi Ho
:
A Comprehensive Security System for Digital Microfluidic Biochips. ITC-Asia 2018: 151-156 - [c38]Juinn-Dar Huang
, Chia-Hung Liu, Wei-Hao Yang:
Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips. VLSI-SoC 2018: 13-18 - 2017
- [j19]Sukanta Bhattacharjee
, Sudip Poddar
, Sudip Roy, Juinn-Dar Huang
, Bhargab B. Bhattacharya:
Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 614-627 (2017) - [c37]Juinn-Dar Huang
, Yi-Hang Chen, Jia-Shin Lu:
Defect-aware synthesis for reconfigurable single-electron transistor arrays. VLSI-SoC 2017: 1-6 - 2016
- [j18]Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang
:
Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints. ACM J. Emerg. Technol. Comput. Syst. 12(4): 37:1-37:15 (2016) - [c36]Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang
, Jing-Yang Jou:
Chain-based pin count minimization for general-purpose digital microfluidic biochips. ASP-DAC 2016: 599-604 - [c35]Yung-Chun Lei, Yi-Ling Chen, Juinn-Dar Huang
:
Reactant cost minimization through target concentration selection on microfluidic biochips. BioCAS 2016: 58-61 - [c34]Yung-Chun Lei, Tung-Hsuan Lin, Juinn-Dar Huang
:
Multi-objective sample preparation algorithm for microfluidic biochips supporting various mixing models. SoCC 2016: 96-101 - 2015
- [j17]Ya-Shih Huang, Han-Yuan Chang, Juinn-Dar Huang
:
TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(8): 1796-1805 (2015) - [j16]Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang
:
Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1429-1440 (2015) - [j15]Chia-Hung Liu, Kuo-Cheng Shen, Juinn-Dar Huang
:
Reactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1918-1927 (2015) - [c33]Chi-Mei Huang, Chia-Hung Liu, Juinn-Dar Huang:
Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers. DATE 2015: 1114-1119 - [c32]Yi-Hang Chen, Yang Chen, Juinn-Dar Huang
:
ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays. VLSI-DAT 2015: 1-4 - 2014
- [j14]Bu-Ching Lin, Juinn-Dar Huang
, Jing-Yang Jou:
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(4): 931-939 (2014) - [j13]Bu-Ching Lin, Ming-En Shih, Juinn-Dar Huang, Jing-Yang Jou:
Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors. J. Inf. Sci. Eng. 30(4): 991-1014 (2014) - [c31]Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang:
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints. DATE 2014: 1-4 - [c30]Juinn-Dar Huang
, Chia-Hung Liu:
Sample preparation for droplet-based microfluidics. ISIC 2014: 364-367 - [c29]Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang
:
Two-staged parallel layer-aware partitioning for 3D designs. VLSI-DAT 2014: 1-4 - 2013
- [j12]Juinn-Dar Huang
, Chia-Hung Liu, Huei-Shan Lin:
Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1484-1494 (2013) - [c28]Chia-Hung Liu, Hao-Han Chang, Tung-Che Liang
, Juinn-Dar Huang
:
Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing. ICCAD 2013: 615-621 - [c27]Chia-Hung Liu, Kuang-Cheng Liu, Juinn-Dar Huang
:
Latency-optimization synthesis with module selection for digital microfluidic biochips. SoCC 2013: 159-164 - [c26]Tsung-Yi Ho
, Juinn-Dar Huang, Paul Pop
:
Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration. SoCC 2013: 316-317 - [c25]Ting-Wei Chiang, Chia-Hung Liu, Juinn-Dar Huang
:
Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips. VLSI-DAT 2013: 1-4 - 2012
- [j11]Juinn-Dar Huang
, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou:
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 559-566 (2012) - [c24]Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang:
Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only). FPGA 2012: 268 - [c23]Juinn-Dar Huang
, Chia-Hung Liu, Ting-Wei Chiang:
Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees. ICCAD 2012: 377-383 - 2011
- [j10]Juinn-Dar Huang
, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu:
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(4): 1151-1155 (2011) - [c22]Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang
, Jing-Yang Jou:
Equivalence checking of scheduling with speculative code transformations in high-level synthesis. ASP-DAC 2011: 497-502 - [c21]Juinn-Dar Huang
, Yi-Hang Chen, Ya-Chien Ho:
Throughput optimization for latency-insensitive system with minimal queue insertion. ASP-DAC 2011: 585-590 - [c20]Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang
:
Architectural exploration of 3D FPGAs towards a better balance between area and delay. DATE 2011: 587-590 - [c19]Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang
:
Layer-Aware Design Partitioning for Vertical Interconnect Minimization. ISVLSI 2011: 144-149 - [c18]Chia-I Chen, Juinn-Dar Huang
:
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family. ISVLSI 2011: 369-370 - 2010
- [j9]Chia-I Chen, Juinn-Dar Huang:
A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1300-1308 (2010) - [j8]Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou:
FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26(5): 1601-1617 (2010) - [c17]Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang
, Jing-Yang Jou:
Expandable MDC-based FFT architecture and its generator for high-performance applications. SoCC 2010: 188-192
2000 – 2009
- 2009
- [j7]Ya-Shih Huang, Yu-Ju Hong, Juinn-Dar Huang:
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3143-3150 (2009) - [j6]Yu-Ru Hong, Juinn-Dar Huang:
Reducing fault dictionary size for million-gate large circuits. ACM Trans. Design Autom. Electr. Syst. 14(2): 27:1-27:14 (2009) - [j5]Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 723-727 (2009) - [c16]Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang:
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. ASP-DAC 2009: 19-24 - [c15]Chia-I Chen, Juinn-Dar Huang:
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. ASP-DAC 2009: 67-72 - 2008
- [j4]Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou:
Verification of Pin-Accurate Port Connections. IEEE Des. Test Comput. 25(5): 478-486 (2008) - [c14]Nan-Shing Li, Juinn-Dar Huang, Han-Jung Huang:
Low power multiplexer tree design using dynamic propagation path control. APCCAS 2008: 838-841 - [c13]Chih-Hui Ting, Juinn-Dar Huang, Yu-Hsiang Kao:
Cycle-time-aware sequential way-access set-associative cache for low energy consumption. APCCAS 2008: 854-857 - [c12]Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang:
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. ASP-DAC 2008: 16-21 - [e1]Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha:
2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008. IEEE 2008, ISBN 978-1-4244-2796-3 [contents] - 2007
- [c11]Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou:
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. ASP-DAC 2007: 165-170 - [c10]Yu-Ru Hong, Juinn-Dar Huang:
Fault Dictionary Size Reduction for Million-Gate Large Circuits. ASP-DAC 2007: 829-834 - 2006
- [c9]Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC 2006: 448-453 - [c8]Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou:
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. ASP-DAC 2006: 600-605 - 2005
- [c7]Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. HLDVT 2005: 87-93 - 2004
- [c6]Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang:
Verification on Port Connections. ITC 2004: 830-836 - 2001
- [j3]Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 251-260 (2001) - 2000
- [j2]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 392-400 (2000)
1990 – 1999
- 1998
- [j1]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang:
On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 634-642 (1998) - [c5]Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC 1998: 712-717 - 1997
- [c4]Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei:
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. ASP-DAC 1997: 259-264 - 1996
- [c3]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD 1996: 13-17 - 1995
- [c2]Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao:
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. DAC 1995: 65-69 - [c1]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD 1995: 359-363
Coauthor Index
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