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"Blockage-avoiding buffered clock-tree synthesis for clock latency-range ..."

Xin-Wei Shih et al. (2010)

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DOI: 10.1109/ASPDAC.2010.5419850

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-01

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  - https://dblp.org/rec/conf/aspdac/ShihCHC10
Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang:
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. ASP-DAC 2010: 395-400

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