default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDEmmanuel Casseau
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j25]Shanshan Wang, Chenglong Xiao, Emmanuel Casseau:
Algorithms with improved delay for enumerating connected induced subgraphs of a large cardinality. Inf. Process. Lett. 183: 106425 (2024)- [c57]Hamza Amara, Cédric Killian, Daniel Chillet, Emmanuel Casseau:
Mitigation of Hardware Trojan in NoC using Delta-Based Compression. SOCC 2024: 1-6 - 2023
- [j24]Minyu Cui
, Angeliki Kritikakou, Lei Mo, Emmanuel Casseau:
Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications. J. Syst. Archit. 134: 102790 (2023) - [j23]Petr Dobiás, Emmanuel Casseau, Oliver Sinnen:
Online fault tolerant energy-aware algorithm for CubeSats. Sustain. Comput. Informatics Syst. 38: 100853 (2023) - [c56]Baptiste Rossigneux, Inna Kucher, Vincent Lorrain, Emmanuel Casseau:
Surround the Nonlinearity: Inserting Foldable Convolutional Autoencoders to Reduce Activation Footprint. ICCV (Workshops) 2023: 1399-1403 - 2022
- [j22]Minyu Cui, Angeliki Kritikakou, Lei Mo, Emmanuel Casseau:
Energy-Efficient Partial-Duplication Task Mapping Under Multiple DVFS Schemes. Int. J. Parallel Program. 50(2): 267-294 (2022) - [c55]Van Long Nguyen Huu, Laurent d'Orazio, Emmanuel Casseau, Julien Lallet:
Cache management in MASCARA-FPGA: from coalescing heuristic to replacement policy. DaMoN 2022: 11:1-11:5 - 2021
- [j21]Petr Dobiás, Emmanuel Casseau, Oliver Sinnen:
Improving the CubeSat reliability thanks to a multiprocessor system using fault tolerant online scheduling. Microprocess. Microsystems 85: 104312 (2021) - [j20]Chenglong Xiao, Shanshan Wang, Wanjun Liu, Xinlin Wang, Emmanuel Casseau:
An Optimal Algorithm for Enumerating Connected Convex Subgraphs in Acyclic Digraphs. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 261-265 (2021) - [c54]Minyu Cui, Angeliki Kritikakou, Lei Mo, Emmanuel Casseau:
Fault-Tolerant Mapping of Real-Time Parallel Applications under multiple DVFS schemes. RTAS 2021: 387-399 - [c53]Van Long Nguyen Huu, Laurent d'Orazio, Emmanuel Casseau, Julien Lallet:
MASCARA-FPGA cooperation model: Query Trimming through accelerators. SSDBM 2021: 203-208 - [c52]Emmanuel Casseau, Petr Dobiás, Oliver Sinnen, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Alessandro Savino, Stefano Di Carlo, Maurizio Rebaudengo, Alberto Bosio:
Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum. VTS 2021: 1-10 - [i1]Shanshan Wang, Chenglong Xiao, Emmanuel Casseau:
An algorithm with improved delay for enumerating connected induced subgraphs of a large cardinality. CoRR abs/2112.07204 (2021) - 2020
- [j19]Van Long Nguyen Huu, Julien Lallet, Emmanuel Casseau, Laurent d'Orazio:
MASCARA (ModulAr Semantic CAching fRAmework) towards FPGA Acceleration for IoT Security Monitoring. Open J. Internet Things 6(1): 14-23 (2020) - [c51]Petr Dobiás, Emmanuel Casseau, Oliver Sinnen:
Evaluation of Fault Tolerant Online Scheduling Algorithms for CubeSats. DSD 2020: 622-629 - [c50]Petr Dobiás, Emmanuel Casseau, Oliver Sinnen:
Fault-Tolerant Online Scheduling Algorithms for CubeSats. PARMA-DITAM@HiPEAC 2020: 3:1-3:6 - [c49]Minyu Cui, Lei Mo, Angeliki Kritikakou, Emmanuel Casseau:
Energy-Aware Partial-Duplication Task Mapping Under Real-Time and Reliability Constraints. SAMOS 2020: 213-227
2010 – 2019
- 2019
- [c48]Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys, Emmanuel Casseau:
Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors. DASIP 2019: 23-28 - 2018
- [c47]Petr Dobiás, Emmanuel Casseau, Oliver Sinnen:
Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems. DASIP 2018: 100-105 - [c46]Petr Dobiás, Emmanuel Casseau, Oliver Sinnen:
Restricted Scheduling Windows for Dynamic Fault-Tolerant Primary/Backup Approach-Based Scheduling on Embedded Systems. SCOPES 2018: 27-30 - 2017
- [j18]Chenglong Xiao, Shanshan Wang, Wanjun Liu, Emmanuel Casseau:
Parallel custom instruction identification for extensible processors. J. Syst. Archit. 76: 149-159 (2017) - [c45]Imran Wali, Emmanuel Casseau, Arnaud Tisserand:
An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy. DASIP 2017: 1-6 - 2016
- [j17]Shanshan Wang, Chenglong Xiao, Wanjun Liu, Emmanuel Casseau:
A comparison of heuristic algorithms for custom instruction selection. Microprocess. Microsystems 45: 176-186 (2016) - [c44]Mai-Thanh Tran, Matthieu Gautier, Emmanuel Casseau:
On the FPGA-Based Implementation of a Flexible Waveform from a High-Level Description: Application to LTE FFT Case Study. CrownCom 2016: 545-557 - [c43]Mai-Thanh Tran, Emmanuel Casseau, Matthieu Gautier:
Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standard. DASIP 2016: 241-242 - 2015
- [j16]Hervé Yviquel, Alexandre Sanchez, Pekka Jääskeläinen, Jarmo Takala, Mickaël Raulet, Emmanuel Casseau:
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs. J. Signal Process. Syst. 80(1): 121-136 (2015) - [c42]Kevin J. M. Martin, Yvan Eustache, Jean-Philippe Diguet, Thanh Dinh Ngo, Emmanuel Casseau, Yaset Oliva:
Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms. DASIP 2015: 1-2 - [c41]Shanshan Wang, Chenglong Xiao, Wanjun Liu, Emmanuel Casseau, Xiao Yang:
Selecting most profitable instruction-set extensions using ant colony heuristic. DASIP 2015: 1-7 - [c40]Jérémy Métairie, Arnaud Tisserand, Emmanuel Casseau:
Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m). ISVLSI 2015: 440-445 - 2014
- [j15]Chenglong Xiao, Emmanuel Casseau, Shanshan Wang, Wanjun Liu:
Automatic custom instruction identification for application-specific instruction set processors. Microprocess. Microsystems 38(8): 1012-1024 (2014) - [c39]Yaset Oliva, Emmanuel Casseau, Kevin J. M. Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel, Mickaël Raulet, Erwan Raffin, Laurent Morin:
Orcc's compa-backend demonstration. DASIP 2014: 1-2 - [c38]Hervé Yviquel, Alexandre Sanchez, Pekka Jääskeläinen, Jarmo Takala, Mickaël Raulet, Emmanuel Casseau:
Efficient software synthesis of dynamic dataflow programs. ICASSP 2014: 4988-4992 - [c37]Chenglong Xiao, Emmanuel Casseau:
Improving high-level synthesis effectiveness through custom operator identification. ISCAS 2014: 161-164 - [c36]Quang-Hoa Le, Emmanuel Casseau, Antoine Courtay:
Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture. ReConFig 2014: 1-6 - 2013
- [j14]Hervé Yviquel, Jani Boutellier, Mickaël Raulet, Emmanuel Casseau:
Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs. Signal Process. Image Commun. 28(10): 1295-1302 (2013) - [c35]Hervé Yviquel, Emmanuel Casseau, Mickaël Raulet, Pekka Jääskeläinen, Jarmo Takala:
Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms. ISPA 2013: 732-737 - 2012
- [j13]Erwan Raffin, Christophe Wolinski, François Charot, Emmanuel Casseau, Antoine Floch, Krzysztof Kuchcinski, Stéphane Chevobbe, Stéphane Guyetant:
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture. Int. J. Embed. Real Time Commun. Syst. 3(1): 1-30 (2012) - [j12]Emmanuel Casseau, Bertrand Le Gal:
Design of multi-mode application-specific cores based on high-level synthesis. Integr. 45(1): 9-21 (2012) - [j11]Chenglong Xiao, Emmanuel Casseau:
Exact custom instruction enumeration for extensible processors. Integr. 45(3): 263-270 (2012) - 2011
- [j10]Bertrand Le Gal, Emmanuel Casseau:
Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. EURASIP J. Adv. Signal Process. 2011 (2011) - [j9]Bertrand Le Gal, Emmanuel Casseau:
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. J. Signal Process. Syst. 62(3): 341-357 (2011) - [c34]Chenglong Xiao, Emmanuel Casseau:
Efficient custom instruction enumeration for extensible processors. ASAP 2011: 211-214 - [c33]Chenglong Xiao, Emmanuel Casseau:
Efficient maximal convex custom instruction enumeration for extensible processors. DASIP 2011: 137-143 - [c32]Chenglong Xiao, Emmanuel Casseau:
An efficient algorithm for custom instruction enumeration. ACM Great Lakes Symposium on VLSI 2011: 187-192 - [c31]Daniel Ménard, Hai-Nam Nguyen, François Charot, Stéphane Guyetant, Jérémie Guillot, Erwan Raffin, Emmanuel Casseau:
Exploiting reconfigurable SWP operators for multimedia applications. ICASSP 2011: 1717-1720 - [c30]Andrei Banciu, Emmanuel Casseau, Daniel Ménard, Thierry Michel:
Stochastic modeling for floating-point to fixed-point conversion. SiPS 2011: 180-185 - [c29]Hervé Yviquel, Emmanuel Casseau, Matthieu Wipliez, Mickaël Raulet:
Efficient multicore scheduling of dataflow process networks. SiPS 2011: 198-203 - 2010
- [j8]Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet:
High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1736-1749 (2010) - [c28]Andrei Banciu, Emmanuel Casseau, Daniel Ménard, Thierry Michel:
A case study of the stochastic modeling approach for range estimation. DASIP 2010: 128-135 - [c27]Cecile Beaumin, Olivier Sentieys, Emmanuel Casseau, Arnaud Carer:
A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design. DASIP 2010: 152-159 - [c26]Erwan Raffin, Christophe Wolinski, François Charot, Krzysztof Kuchcinski, Stéphane Guyetant, Stéphane Chevobbe, Emmanuel Casseau:
Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture. DASIP 2010: 168-175
2000 – 2009
- 2009
- [c25]Daniel Ménard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David:
Reconfigurable Operator Based Multimedia Embedded Processor. ARC 2009: 39-49 - [c24]Shafqat Khan, Emmanuel Casseau, Daniel Ménard:
Reconfigurable SWP Operator for Multimedia Processing. ASAP 2009: 199-202 - [c23]Bertrand Le Gal, Emmanuel Casseau:
Automated multimode system design for high performance DSP applications. EUSIPCO 2009: 1289-1293 - [c22]Emmanuel Casseau, Bertrand Le Gal:
High-level synthesis for the design of FPGA-based signal processing systems. ICSAMOS 2009: 25-32 - 2008
- [j7]Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina:
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau. Tech. Sci. Informatiques 27(9-10): 1129-1154 (2008) - [j6]Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet:
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1454-1464 (2008) - 2007
- [j5]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
Constrained algorithmic IP design for system-on-chip. Integr. 40(2): 94-105 (2007) - [c21]Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy:
Synthesis of Multimode digital signal processing systems. AHS 2007: 318-325 - [c20]Sylvain Huet, Sébastien Le Nours, Olivier Pasquier, Emmanuel Casseau:
Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications. FDL 2007: 177-184 - [c19]Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin:
A design flow dedicated to multi-mode architectures for DSP applications. ICCAD 2007: 604-611 - [c18]Bertrand Le Gal, Lilian Bossuet, Shafqat Khan, Emmanuel Casseau:
HLS design flow for the synthesis of multimode systems under multiple constraints. ICECS 2007: 314-317 - 2006
- [j4]Guillaume Savaton, Emmanuel Casseau, Eric Martin:
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. Signal Process. 86(7): 1375-1399 (2006) - [j3]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. 5(1): 29-53 (2006) - [j2]Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin:
G729 Voice Decoder Design. J. VLSI Signal Process. 42(2): 173-184 (2006) - [c17]Sylvain Huet, Emmanuel Casseau, Olivier Pasquier:
A Computation Core for Communication Refinement of Digital Signal Processing Algorithms. DSD 2006: 240-250 - [c16]Sylvain Huet, Emmanuel Casseau, Olivier Pasquier, Sébastien Le Nours:
Hardware Communication Refinement in Digital Signal Processing. FDL 2006: 177-185 - [c15]Bertrand Le Gal, Emmanuel Casseau:
IP Generation Targeting Multiple Bit-Width Standards. ICECS 2006: 784-787 - [c14]Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau:
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. SiPS 2006: 280-285 - [c13]Bertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau:
Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems. SoCC 2006: 175-178 - 2005
- [c12]Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno:
Hardware Virtual Components Compliant with Communication System Standards. DSD 2005: 88-95 - [c11]Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin:
C-based rapid prototyping for digital signal processing. EUSIPCO 2005: 1-4 - [c10]Bertrand Le Gal, Emmanuel Casseau, Eric Martin:
Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. EUSIPCO 2005: 1-4 - [c9]Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin:
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. ISVLSI 2005: 268-269 - [c8]Sylvain Huet, Emmanuel Casseau, Olivier Pasquier:
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. IEEE International Workshop on Rapid System Prototyping 2005: 240-243 - 2004
- [j1]Emmanuel Casseau, Christophe Jégo, Eric Martin:
Synthèse architecturale d'applications temps réel pour technologies submicroniques. Tech. Sci. Informatiques 23(1): 35-66 (2004) - [c7]Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin:
Reed-Solomon behavioral virtual component for communication systems. ISCAS (4) 2004: 173-176 - 2002
- [c6]Emmanuel Casseau:
SoC design using behavioral level virtual components. ICECS 2002: 497-500 - 2001
- [c5]Emmanuel Casseau, Christophe Jégo, Eric Martin:
Architectural synthesis of digital signal processing applications dedicated to submicron technologies. ICECS 2001: 535-538
1990 – 1999
- 1999
- [c4]Christophe Jégo, Emmanuel Casseau, Eric Martin:
Architectural Synthesis with Interconnection Cost Control. VLSI 1999: 509-520 - 1996
- [c3]Eric Lüthi, Emmanuel Casseau:
High Rate Soft Output Viterbi Decoder. ED&TC 1996: 315-319 - [c2]Emmanuel Casseau, Eric Lüthi:
Architecture of a high-rate VLSI Viterbi decoder. ICECS 1996: 21-24 - 1994
- [c1]Emmanuel Casseau, Dominique Degrugillier:
A Linear Systolic Array for LU Decomposition. VLSI Design 1994: 353-358
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-20 22:00 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
