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Mounir Benabdenbi
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2020 – today
- 2021
- [c26]Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory:
FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method. ISVLSI 2021: 170-175 - 2020
- [c25]Noureddine Ait Said
, Mounir Benabdenbi, Katell Morin-Allory:
FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach. DTIS 2020: 1-6
2010 – 2019
- 2019
- [c24]Ali Skaf, Mona Ezzadeen, Mounir Benabdenbi, Laurent Fesquet:
On-Line Adjustable Precision Computing. DTIS 2019: 1-5 - 2018
- [j6]Lorena Anghel
, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola
, Elena Ioana Vatajelu
:
Test and Reliability in Approximate Computing. J. Electron. Test. 34(4): 375-387 (2018) - 2015
- [c23]Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel:
Application-independent testing of multilevel interconnect in mesh-based FPGAs. DTIS 2015: 1-6 - 2014
- [j5]Michael G. Dimopoulos, Yi Gang, Lorena Anghel
, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. Microprocess. Microsystems 38(6): 620-635 (2014) - [j4]Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux:
On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1364-1376 (2014) - [c22]Lorena Anghel, Mounir Benabdenbi, Frédéric Pétrot:
System on chip project: Integration of a Motion-JPEG video decoder. EWME 2014: 167-170 - [c21]Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel:
Cost-efficient of a cluster in a mesh SRAM-based FPGA. IOLTS 2014: 75-80 - [c20]Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner
, Lorena Anghel
, Habib Mehrez, Emna Amouri, Zied Marrakchi:
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI 2014: 553-558 - 2013
- [c19]Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
:
BIST for logic and local interconnect resources in a novel mesh of cluster FPGA. DFTS 2013: 296-301 - [c18]Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner
, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi:
A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT 2013: 434-437 - [c17]Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel
, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. IOLTS 2013: 7-12 - 2012
- [j3]Vladimir Pasca, Lorena Anghel
, Michael Nicolaidis, Mounir Benabdenbi:
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems. J. Electron. Test. 28(1): 137-150 (2012) - [j2]Vladimir Pasca, Lorena Anghel
, Mounir Benabdenbi:
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis. J. Electron. Test. 28(6): 817-829 (2012) - [c16]Vladimir Pasca, Saif-Ur Rehman, Lorena Anghel
, Mounir Benabdenbi:
Efficient link-level error resilience in 3D NoCs. DDECS 2012: 127-132 - 2011
- [c15]Vladimir Pasca, Lorena Anghel
, Mounir Benabdenbi:
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis. LATW 2011: 1-6 - [c14]Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux:
Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure. VTS 2011: 229-234 - 2010
- [c13]Etienne Faure, Gabriel Marchesan Almeida, Mounir Benabdenbi, Pascal Benoit, Fabien Clermidy, François Pêcheux, Gilles Sassatelli, Lionel Torres:
An in-memory monitoring database for self adaptive MP2SoCs. DASIP 2010: 97-104 - [c12]Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi:
Fault tolerant communication in 3D integrated systems. DSN Workshops 2010: 131-135 - [c11]Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi:
Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. ETS 2010: 258 - [c10]Etienne Faure, Mounir Benabdenbi, François Pêcheux:
Distributed online software monitoring of manycore architectures. IOLTS 2010: 56-61 - [c9]Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi:
Configurable serial fault-tolerant link for communication in 3D integrated systems. IOLTS 2010: 115-120 - [c8]Zhen Zhang, Alain Greiner, Mounir Benabdenbi:
Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components. IOLTS 2010: 194-196
2000 – 2009
- 2009
- [c7]Mounir Benabdenbi, François Pêcheux, Etienne Faure:
On-line test and monitoring of multi-processor SoCs: A software-based approach. LATW 2009: 1-6 - 2007
- [c6]Matthieu Tuna, Mounir Benabdenbi, Alain Greiner:
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. VTS 2007: 447-454 - 2006
- [c5]Alain Greiner, Frédéric Pétrot, M. Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, Raphaël Labayrade:
MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation. ReCoSoC 2006: 24-30 - 2004
- [c4]Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna:
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores. DATE 2004: 712-713 - 2002
- [j1]Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki:
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. J. Electron. Test. 18(4-5): 455-473 (2002) - 2001
- [c3]Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki:
Testing TAPed cores and wrapped cores with the same test access mechanism. DATE 2001: 150-155 - 2000
- [c2]Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki:
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip. DATE 2000: 141-145 - [c1]Walid Maroufi, Mounir Benabdenbi, Meryem Marzouki:
Solving the I/O Bandwidth Problem in System on a Chip Testing. SBCCI 2000: 9-14
Coauthor Index
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