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ORCID24th LATS 2023: Veracruz, Mexico
- 24th IEEE Latin American Test Symposium, LATS 2023, Veracruz, Mexico, March 21-24, 2023. IEEE 2023, ISBN 979-8-3503-2597-3
- Pooja Choudhary, Lava Bhargava
, Masahiro Fujita, Virendra Singh:
LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error. 1-2 - Pablo A. Petrashin, Walter J. Lancioni, Agustin Laprovitta, Fortunato Dualibe, Juan Luis Castagnola:
Effect of Vth shifting in CMOS Transistors under radiation conditions when applying OBT: A case study. 1-4 - Xinhui Lai, Maksim Jenihhin:
Analyzing Side-Channel Attack Vulnerabilities at RTL. 1-2 - Erik Larsson:
Co-optimization of security and accessibility to on-chip instruments. 1-2 - Sonali Shukla, Bhavika Ranjeet Kumar, Virendra Singh:
SSSN: Secured Streaming Scan Network. 1-6 - Esther Goudet, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche:
Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. 1-6 - Edilson Filho, Jarbas Silveira, César A. M. Marcon:
Blockchain Applied In Decentralization of Ground Stations To Educational Nanosatellites. 1-5 - Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio:
A Fault Injection Framework for AI Hardware Accelerators. 1-6 - Hans-Joachim Wunderlich, Hanieh Jafarzadeh, Alexandra Kourfali, Natalia Lylina, Zahra Paria Najafi-Haghi:
Test Aspects of System Health State Monitoring. 1-2 - Thibault Vayssade, Florence Azaïs, Laurent Latorre, François Lefèvre:
Low-cost digital solution for production test of ZigBee transmitters Special Session "AMS-RF testing". 1-2 - Foisal Ahmed, Maksim Jenihhin:
Holistic IJTAG-based External and Internal Fault Monitoring in UAVs. 1-6 - Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli:
A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates. 1-6 - Christo A. Lara, Maximiliano Fragoso, Luis Manuel Juárez, Leonardo Barboni, Rigoberto Reyes, Ricardo Vázquez, Julio Pérez Acle, Saúl de la Rosa:
Fault Tolerant Architecture Design of a CubeSat Command and Data Handling System. 1-6 - Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero:
Feature Selection for Cost Reduction In MCU Performance Screening. 1-6 - Chandramouli N. Amarnath, Abhijit Chatterjee:
Error Resilient Neuromorphic Systems Using Embedded Predictive Neuron Checks. 1-2 - Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán:
Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. 1-2 - Thiago Santos Copetti, A. Castelnuovo, Tobias Gemmeke, Letícia Maria Veiras Bolzani:
Evaluating a New RRAM Manufacturing Test Strategy. 1-6 - Adit D. Singh:
Silent Error Corruption: The New Reliability and Test Challenge. 1-2 - G. Govarini, Annachiara Ruospo, Edgar E. Sánchez:
A Fast Reliability Analysis of Image Segmentation Neural Networks Exploiting Statistical Fault Injections. 1-6 - Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán:
Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation. 1-2 - Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, Matteo Sonza Reorda:
Analyzing the Architectural Impact of Transient Fault Effects in SFUs of GPUs. 1-6 - Pratishtha Agnihotri, Lawrence M. Schlitt, Priyank Kalla, Steve Blair:
Abstractions for Modeling the Effects of Wall Surface Roughness in Silicon Photonic Microring Resonators. 1-6 - Paolo Bernardi, Gabriele Filipponi, Tommaso Foscale, Giorgio Insinga:
Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests. 1-2 - Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Veiras Bolzani Poehls, Rainer Leupers:
Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware. 1-6 - Francesco Angione, Paolo Bernardi, Riccardo Cantoro, Nicola Di Gruttola Giardino, Davide Piumatti, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre:
On the integration and hardening of Software Test Libraries in Real-Time Operating Systems. 1-6
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