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ORCID23rd IOLTS 2017: Thessaloniki, Greece
- 23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, Thessaloniki, Greece, July 3-5, 2017. IEEE 2017, ISBN 978-1-5386-0352-9
- Ahmed Ibrahim
, Hans G. Kerkhoff:
A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687. 1-2 - Alexander Klockmann, Georg Georgakos, Michael Gössel:
A new 3-bit burst-error correcting code. 3-4 - Alexandra Kourfali, Amit Kulkarni, Dirk Stroobandt:
SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs. 5-8 - Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer:
Assessment of the amplitude-duration criterion for SET/SEU robustness evaluation. 9-12 - Mohamed Makhlouf, Diana Goller, Lutz Gendrisch, Stephan Kolnsberg, Franz Vogt, Alexander Utz, Dirk Weiler, Holger Vogt:
Automating wafer-level test of uncooled infrared detectors using wafer-prober. 13-16 - Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura:
Controller augmentation and test point insertion at RTL for concurrent operational unit testing. 17-20 - Stefano Esposito, Massimo Violante:
Deterministic network on chip for deploying real time applications on many-core processors. 21-24 - Theodoros Toulas, Spyros Tragoudas:
Diagnosis with transition faults on embedded segments. 25-27 - Issam Nofal, Adrian Evans, Anlin He, Gang Guo, Yuanqing Li, Li Chen, Rui Liu, Haibin Wang, Mo Chen, Sang H. Baeg, Shi-Jie Wen, Richard Wong:
BPPT - Bulk potential protection technique for hardened sequentials. 28-32 - Ghaith Bany Hamad, Ghaith Kazma, Otmane Aït Mohamed, Yvon Savaria:
Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT. 33-38 - Mohamed A. Abufalgha, Alex Bystrov:
Design-time reliability evaluation for digital circuits. 39-44 - Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis:
Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms. 45-50 - George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Charalampos Magdalinos, Dimitris Gizopoulos:
Voltage margins identification on commercial x86-64 multicore microprocessors. 51-56 - Xiaobing Shi, Nicola Nicolici:
A generic embedded sequence generator for constrained-random validation with weighted distributions. 57-62 - Christophe Eychenne, Yervant Zorian:
An effective functional safety infrastructure for system-on-chips. 63-66 - Paolo Bernardi, Marco Restifo, Ernesto Sánchez, Matteo Sonza Reorda:
On the in-field test of embedded memories. 67-70 - Hanna Shaheen, Gabriele Boschi, Gurgen Harutyunyan, Yervant Zorian:
Advanced ECC solution for automotive SoCs. 71-73 - Jing Ye, Yu Hu, Xiaowei Li:
VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance. 74-79 - Koyo Suzuki, Katsuyoshi Miura, Koji Nakamae:
NBTI/PBTI tolerant arbiter PUF circuits. 80-84 - Alexis Krakovinsky, Marc Bocquet, Romain Wacquez, Jean Coignus, Jean-Michel Portal:
Thermal laser attack and high temperature heating on HfO2-based OxRAM cells. 85-89 - Antonio Rubio, Manuel Escudero, Peyman Pouyan:
Reliability issues in RRAM ternary memories affected by variability and aging mechanisms. 90-92 - Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota:
6T CMOS SRAMs reliability monitoring through stability measurements. 93-95 - Ivan Miro Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart:
In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. 96-99 - Yiorgos Sfikas, Yiorgos Tsiatouhas:
Variation tolerant BTI monitoring in SRAM cells. 100-105 - Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix:
Dynamic aging compensation and Safety measures in Automotive environment. 106-112 - P. Madhukar Reddy, Stavros Hadjitheophanous, Vassos Soteriou, Paul V. Gratz, Maria K. Michael:
Minimal exercise vector generation for reliability improvement. 113-119 - Manuel Escudero-Lopez, Francesc Moll, Antonio Rubio, Ioannis Vourkas:
An on-line test strategy and analysis for a 1T1R crossbar memory. 120-125 - Elena-Ioana Vatajelu, Lorena Anghel:
Reliability analysis of MTJ-based functional module for neuromorphic computing. 126-131 - Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh:
Revisiting random access scan for effective enhancement of post-silicon observability. 132-137 - Alessandro Vallero, Dimitris Gizopoulos, Stefano Di Carlo:
SIFI: AMD southern islands GPU microarchitectural level fault injector. 138-144 - Dan Alexandrescu, Adrian Evans, Maximilien Glorieux, Issam Nofal:
EDA support for functional safety - How static and dynamic failure analysis can improve productivity in the assessment of functional safety. 145-150 - Yukiya Miura, Takuya Yamamoto:
Simulation-based analysis of FF behavior in presence of power supply noise. 151-156 - Ulrich Backhausen, Oscar Ballan, Paolo Bernardi, Sergio de Luca, Julie Henzler, Thomas Kern, Davide Piumatti, Thomas Rabenalt, Krishnapriya Chakiat Ramamoorthy, Ernesto Sánchez, Alessandro Sansonetti, Rudolf Ullmann, Federico Venini, Robert Wiesner:
Robustness in automotive electronics: An industrial overview of major concerns. 157-162 - Fangan-Yssouf Dosso, Pascal Véron:
Cache timing attacks countermeasures and error detection in Euclidean addition chains based scalar multiplication algorithm for elliptic curves. 163-168 - Batya Karp, Yerucham Berkowitz, Osnat Keren:
Jamming resistant encoding for non-uniformly distributed information. 169-173 - Luca Sterpone, Luca Boragno:
Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs. 174-179 - Da Cheng, Amitava Majumdar, Xiaobao Wang, Nui Chong:
Field profiling & monitoring of payload transistors in FPGAs. 180-185 - Shahin Tajik, Julian Fietkau, Heiko Lohrke, Jean-Pierre Seifert, Christian Boit:
PUFMon: Security monitoring of FPGAs using physically unclonable functions. 186-191 - Jacob A. Abraham, Suvadeep Banerjee, Abhijit Chatterjee:
Design of efficient error resilience in signal processing and control systems: From algorithms to circuits. 192-195 - Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle:
Reliability of computing systems: From flip flops to variables. 196-198 - Petr Pfeifer, Farnoosh Hosseinzadeh, Heinrich Theodor Vierhaus:
On comparison of robust configurable FPGA encoders for dependable industrial communication systems. 199-200 - Jose Angel Miranda, Anna Vaskova, Marta Portela-García, Mario García-Valderas, Celia López-Ongil:
On-line testing of sensor networks: A case study. 201-202 - Felix Mühlbauer, Lukas Schröder, Mario Schölzel:
Handling of permanent faults in dynamically scheduled processors. 203-204 - Jing Ye, Yue Gong, Yu Hu, Xiaowei Li:
Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack. 205-206 - Javad Talafy, Hamid R. Zarandi:
Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution. 207-208 - Harsh N. Patel, Benton H. Calhoun, Randy W. Mann:
Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications. 209-210 - Toral Shah, Anzhela Yu. Matrosova, Virendra Singh:
Test pattern generation to detect multiple faults in ROBDD based combinational circuits. 211-212 - Anjela Yu. Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko:
Trojan circuits preventing and masking in sequential circuits. 213-214 - Masaru Oya, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojan detection and classification based on steady state learning. 215-220 - Nikolaos Karousos, Konstantinos Pexaras, Irene G. Karybali, Emmanouil Kalligeros:
Weighted logic locking: A new approach for IC piracy protection. 221-226 - Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojans classification for gate-level netlists using multi-layer neural networks. 227-232 - Mohammad Saber Golanbari, Mehdi Baradaran Tahoori:
Design flows for resilient energy-efficient systems. 233-236 - Alexander Schöll, Claus Braun, Hans-Joachim Wunderlich:
Energy-efficient and error-resilient iterative solvers for approximate computing. 237-239 - Robert Schmidt, Alberto García Ortiz, Görschwin Fey:
Temporal redundancy latch-based architecture for soft error mitigation. 240-243 - Adedotun Adeyemo, Abusaleh M. Jabir, Jimson Mathew, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi:
Reliable gas sensing with memristive array. 244-246 - Florian Cacho, Ahmed Benhassain, Riddhi Jitendrakumar Shah, Souhir Mhira, Vincent Huard, Lorena Anghel:
Investigation of critical path selection for in-situ monitors insertion. 247-252 - Woongrae Kim, Taizhi Liu, Linda Milor:
On-line monitoring of system health using on-chip SRAMs as a wearout sensor. 253-258 - Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh:
Instruction-based self-test for delay faults maximizing operating temperature. 259-264 - Stefan Scharoba, Heinrich Theodor Vierhaus:
Fast power overhead prediction for hardware redundancy-based fault tolerance. 265-270 - Md Imran Momtaz, Suvadeep Banerjee, Abhijit Chatterjee:
Probabilistic error detection and correction in switched capacitor circuits using checksum codes. 271-276
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