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ORCIDKai Yu 0016
Person information
- affiliation: Intel Corporation, Hillsboro, OR, USA
- affiliation (PhD 2009): Carnegie Mellon University, Pittsburgh, PA, USA
Other persons with the same name
- Kai Yu — disambiguation page
- Kai Yu 0001 — Baidu Inc., Institute of Deep Learning, Beijing, China (and 3 more)
- Kai Yu 0002 — Royal Institute of Technology, Stockholm, Sweden
- Kai Yu 0003
![[0000-0002-4778-4389]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-4778-4389")
— University of Minnesota, Department of Biomedical Engineering, Minneapolis, MN, USA - Kai Yu 0004 — Shanghai Jiao Tong University, Computer Science and Engineering Department, China (and 1 more)
- Kai Yu 0005 — Zhejiang University, State Key Laboratory of Industrial Control Technology, Hangzhou, China
- Kai Yu 0006 — Beijing Normal University, School of Geography, China (and 1 more)
- Kai Yu 0007 — Hohai University, College of Oceanography, Nanjing, China (and 2 more)
- Kai Yu 0008 — Guangdong University of Technology, School of Information Engineering, School of Integrated Circuits, China (and 1 more)
- Kai Yu 0009 — Soochow University, School of Electronics and Information Engineering, Jiangsu, China (and 1 more)
- Kai Yu 0010 — Nanjing University, School of Electronic Science and Engineering, China
- Kai Yu 0011 — Sun Yat-Sen University, Cancer Center, State Key Laboratory of Oncology in South China, Collaborative Innovation Center for Cancer Medicine, China
- Kai Yu 0012 — Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology, China
- Kai Yu 0013 — Beihang University, School of Computer Science and Engineering, State Key Laboratory of Software Development Environment, China
- Kai Yu 0014 — Nanjing University of Aeronautics and Astronautics, College of Electronic and Information Engineering, China
- Kai Yu 0015 — Shandong University of Science and Technology, College of Mining and Safety Engineering, Qingdao, China
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2020 – today
- 2024
[c6]Jihwan Kim, Ariel Cohen, Mike Peng Li, Ajay Balankutty, Sandipan Kundu, Ahmad Khairi, Yoel Krupnik, Yoav Segal, Marco Cusmai, Dror Lazar, Ari Gordon, Noam Familia, Kai Yu, Yutao Liu, Matthew Beach, Priya Wali, Hsinho Wu, Masashi Shimanouchi, Jenny Xiaohong Jiang, Zhiguo Qian, Kemal Aygun, Itamar Levin, Frank O'Mahony:
Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging. CICC 2024: 1-8- 2022
- [j2]Jihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen T. Kim, Yutao Liu, Savyasaachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yoav Segal, Yongping Fan, Peng Li, Frank O'Mahony:
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. IEEE J. Solid State Circuits 57(1): 6-20 (2022) - 2021
- [c5]Jihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen Kim, Yutao Liu, Savyassachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yongping Fan, Frank O'Mahony:
8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS. ISSCC 2021: 126-128
2010 – 2019
- 2019
- [j1]Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Dan Shi, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET. IEEE J. Solid State Circuits 54(1): 29-42 (2019) - 2018
- [c4]Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. ISSCC 2018: 102-104 - 2015
- [c3]Rajeev K. Dokania, Alexandra M. Kern, Mike He, Adam C. Faust, Richard Tseng, Skyler Weaver, Kai Yu, Christiaan Bil, Tao Liang, Frank O'Mahony:
10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS. ISSCC 2015: 1-3 - [c2]Jihwan Kim, Ajay Balankutty, Amr Elshazly, Yan-Yu Huang, Hang Song, Kai Yu, Frank O'Mahony:
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. ISSCC 2015: 1-3 - 2014
- [c1]Amr Elshazly, Ajay Balankutty, Yan-Yu Huang, Kai Yu, Frank O'Mahony:
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. VLSIC 2014: 1-2
Coauthor Index
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