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2020 – today
- 2024
[c32]Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, Sehoon Park, Jorge-Luis Lagos
, Nereo Markulic, Jan Craninckx:
22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. ISSCC 2024: 396-398- [c31]Jorge Lagos, Pratap Tumkur Renukaswamy, Nereo Markulic, Ewout Martens, Jan Craninckx:
A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS. VLSI Technology and Circuits 2024: 1-2 - [c30]Nereo Markulic, Johan Nguyen, Jorge Luis Lagos-Benites, Ewout Martens, Jan Craninckx:
A 10GS/s Hierarchical Time-Interleaved ADC for RF-Sampling Applications. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j22]Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Rui Paulo Martins, Yan Zhu, Jan Craninckx, Chi-Hang Chan:
A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4679-4691 (2023) - [c29]Ewout Martens, Nereo Markulic, Jorge Luis Lagos-Benites, Jan Craninckx:
Calibration Techniques for Optimizing Performance of High-Speed ADCs. CICC 2023: 1-8 - [c28]Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx:
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. ESSCIRC 2023: 389-392 - [c27]Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx:
A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET. MWSCAS 2023: 895-899 - 2022
- [j21]Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx:
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits 57(4): 1112-1124 (2022) - [j20]Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. IEEE J. Solid State Circuits 57(6): 1673-1683 (2022) - [j19]Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits 57(7): 2068-2077 (2022) - 2021
- [j18]Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits 56(4): 1227-1240 (2021) - [j17]Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx:
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits 56(8): 2360-2374 (2021) - [j16]Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2813-2826 (2021) - [j15]Keigo Bunsen, Ewout Martens, Davide Dermit, Jan Craninckx:
A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 592-596 (2021) - [c26]Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC 2021: 207-210 - [c25]Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx:
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits 2021: 1-2 - [c24]Ewout Martens, Davide Dermit, Mithlesh Shrivas, Shun Nagata, Jan Craninckx:
A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW. VLSI Circuits 2021: 1-2 - [c23]Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC. VLSI Circuits 2021: 1-2 - 2020
- [c22]Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC 2020: 254-256 - [c21]Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j14]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits 54(2): 403-416 (2019) - [j13]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits 54(3): 646-658 (2019) - [j12]Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits 54(4): 1059-1073 (2019) - [j11]Shiwei Wang, Carolina Mora Lopez, Seyed Kasra Garakoui, Ho Sung Chun, Didac Gomez Salinas, Wim Sijbers, Jan Putzeys, Ewout Martens, Jan Craninckx, Nick Van Helleputte:
A Compact Quad-Shank CMOS Neural Probe With 5, 120 Addressable Recording Sites and 384 Fully Differential Parallel Channels. IEEE Trans. Biomed. Circuits Syst. 13(6): 1625-1634 (2019) - [c20]Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx:
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC 2019: 58-60 - [c19]Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC 2019: 68-70 - 2018
- [j10]Ewout Martens, Benjamin P. Hershberg, Jan Craninckx:
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. IEEE J. Solid State Circuits 53(4): 1161-1171 (2018) - [c18]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC 2018: 1-4 - [c17]Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits 2018: 215-216 - 2016
- [j9]Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits 51(7): 1593-1606 (2016) - [j8]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits 51(12): 3078-3092 (2016) - [c16]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC 2016: 176-177 - 2015
- [j7]Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx:
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. IEEE J. Solid State Circuits 50(9): 2002-2011 (2015) - [c15]Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. ESSCIRC 2015: 80-83 - [c14]Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx:
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. ESSCIRC 2015: 164-167 - 2014
- [j6]Barend van Liempd, Jonathan Borremans, Ewout Martens, Sungwoo Cha, Hans Suys, Bob Verbruggen, Jan Craninckx:
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration. IEEE J. Solid State Circuits 49(8): 1815-1826 (2014) - 2013
- [c13]Barend van Liempd, Jonathan Borremans, Sungwoo Cha, Ewout Martens, Hans Suys, Jan Craninckx:
IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm. CICC 2013: 1-4 - 2012
- [j5]Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert:
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits 47(4): 990-1002 (2012)
2000 – 2009
- 2009
- [j4]Ewout Martens, Georges G. E. Gielen:
ANTIGONE: Top-down creation of analog-to-digital converter architectures. Integr. 42(1): 10-23 (2009) - 2008
- [j3]Ewout Martens, Georges G. E. Gielen:
Classification of analog synthesis tools based on their architecture selection mechanisms. Integr. 41(2): 238-252 (2008) - 2007
- [b1]Ewout Martens:
High-level modeling and synthesis of analog integrated systems ; Hoog-niveau synthese van analoge geïntegreerde systemen. Katholieke Universiteit Leuven, Belgium, 2007 - [c12]Georges G. E. Gielen, Tom Eeckelaert, Ewout Martens, Trent McConaghy:
Automated synthesis of complex analog circuits. ECCTD 2007: 20-23 - 2006
- [j2]Ewout Martens, Georges G. E. Gielen:
Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 924-932 (2006) - [c11]Ewout Martens, Georges G. E. Gielen:
Top-down heterogeneous synthesis of analog and mixed-signal systems. DATE 2006: 275-280 - [c10]Ewout Martens, Georges G. E. Gielen:
Generic Behavioral Modeling of Analog and Mixed-Signal Systems. FDL 2006: 15-23 - [c9]Ewout Martens, Georges G. E. Gielen:
A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers. ISCAS 2006 - 2005
- [c8]Ewout Martens, Georges G. E. Gielen:
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series. DATE 2005: 120-125 - [c7]Ewout Martens, Georges G. E. Gielen:
Behavioral modeling and simulation of weakly nonlinear sampled-data systems. ISCAS (3) 2005: 2247-2250 - 2004
- [j1]Georges G. E. Gielen, Kenneth Francken, Ewout Martens, Martin Vogels:
An analytical integration method for the simulation of continuous-time ΔΣ modulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 389-399 (2004) - [c6]Ewout Martens, Georges G. E. Gielen:
High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models. ASP-DAC 2004: 51-56 - [c5]Ewout Martens, Georges G. E. Gielen:
A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design. DATE 2004: 436-441 - 2003
- [c4]Ewout Martens, Georges G. E. Gielen:
A Model of Computation for Continuous-Time ?-? Modulators. DATE 2003: 10162-10167 - 2002
- [c3]Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen:
DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators. DATE 2002: 1110 - [c2]Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen:
A behavioral simulation tool for continuous-time delta sigma modulators. ICCAD 2002: 234-239 - [c1]Martin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen:
Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration. ISCAS (4) 2002: 237-240
Coauthor Index
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