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"A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage ..."
Shiva Kiran et al. (2019)
- Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo:
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. IEEE J. Solid State Circuits 54(3): 659-671 (2019)
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